Adam Erickson is a Verification Methodologist at Siemens EDA, where he’s served as a principal developer of the OVM, UVM, and UVM Connect. Since earning his Masters in Engineering Sciences at Dartmouth College, Adam has collected 22 years experience in design, verification, and implementation of integrated circuits for companies large and small. He has committed the last 16 of those years developing EDA software and methodological solutions for increasing productivity and reuse in verification. He has authored articles for Verification Horizons and published several conference papers, including Best Paper on a cost-benefit analysis of UVM macros at DVCon 2010. When he’s not improving existing solutions or developing ideas for new ones, Adam can often be found teaching their virtues to others. Adam is currently the primary technical representative for Siemens EDA on the Accellera VIP-TSC, the committee responsible for UVM standardization.
