Questa VIP supports a large library of industry-standard protocol and memory interfaces and devices. It includes standard SystemVerilog UVM components using a consistent, common architecture that allows rapid deployment of multiple protocols or memory models within a verification team. Test plans, compliance tests, test sequences, and protocol coverage are all included as SystemVerilog and XML source code, allowing easy reuse, extension, and debug. All Questa VIP components include a comprehensive set of protocol checks, error injection, and debug capabilities.
*All Questa Verification IPs can also be deployed as monitor.
*All Questa Verification IPs support complete UVM testbench configuration and industry-standard simulators.