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Design and Verification Languages

Design and Verification Languages

Verification languages are the foundation of the very dynamic electronics industry. Industry continually demands improvements in the process of providing differentiated products into their markets. These verification language courses provide in-depth knowledge of key design and verification languages so that you can identify and deploy them in your upcoming projects.

AMS Verification

Nearly all of today's chips contain Analog/Mixed-Signal circuits. Although these often constitute only 25% of the total die, they are often 100% of the product differentiation and also, unfortunately, 80% of the problems in actually getting the chip to market in a cost effective and timely way. Better design – executed more productively – is critical for today's sophisticated chips and SoC's.

These courses will introduce advanced Mixed-Signal verification techniques and help leaners understand how to choose the best methodology for a given design and execute it efficiently. These courses will cover a general understanding of Mixed-Signal design types and design verification requirements with a high-level overview of verification choices and results.

The target audience of these courses is the Mixed-Signal – and/or CAD – Engineers or Managers looking for ways to manage complex Mixed-Signal design structures by understanding the various available techniques addressing the challenges in Mixed-Signal SoC designs.

AMS Design Configuration Schemes

AMS Design Configuration Schemes Course | Subject Matter Expert - Ahmed Eisawy | Design and Verification Languages Topic

This course will introduce the various techniques available in AMS design environment to help understand how to efficiently utilize them.

Improve AMS Verification Performance

Improve AMS Verfiication Performance Course | Subject Matter Expert - Ahmed Eisawy |  Design and Verification Languages Topic

This course will introduce the various modeling practices available in AMS design environment to help understand how to efficiently utilize them.

Improve AMS Verification Quality

Improve AMS Verfiication Quality Course | Subject Matter Expert - Ahmed Eisawy |  Design and Verification Languages Topic

This course will introduce some methodologies available in AMS design environments that could help quantify the quality of the AMS verification process.

VHDL-2008

VHDL-2008 matters because it facilitates advanced verification, adds reusable data structures, simplifies RTL coding and adds fixed and floating point math packages. VHDL-2008 is the largest change to VHDL since 1993; this Verification Academy course is designed to explain the value of the new VHDL-2008 improvements for both Design and Verification Engineers. It is time to start using the new language features to simplify your RTL coding and facilitate the creation of advanced verification environments.

VHDL-2008 Why It Matters

VHDL-2008 Why It Matters Course | Subject Matter Expert - Jim Lewis | Design and Verification Languages Topic

VHDL-2008 matters because it facilitates advanced verification, adds reusable data structures, simplifies RTL coding and adds fixed and floating point math packages.

VHDL-2008: Why It Matters  Why It Matters

by Jim Lewis, SynthWorks VHDL Training

VHDL-2008 (IEEE 1076-2008) is here! It is time to start using the new language features to simplify your RTL coding and facilitate the creation of advanced verification environments. VHDL-2008 is the largest change to VHDL since 1993.

An abbreviated list of changes includes:

  • Enhanced Generics = better reuse.
  • Assertion language (PSL) = better verification.
  • Fixed and floating point packages = better math.
  • Composite types with elements that are unconstrained arrays = better data structures.
  • Hierarchical reference = easier verification.
  • Simplified Sensitivity List = less errors and work.
  • Simplified conditionals (if, ...) = less work.
  • Simplified case statements = less work.

Read more →

Presented by SynthWorks

Comprehensive VHDL Introduction

Learn VHDL syntax plus the basics of RTL and testbench coding.
Students get VHDL hardware experience with our FPGA based lab board.

VHDL Testbenches and Verification

Learn the latest VHDL verification techniques including transaction-based testing, bus functional modeling, self-checking, data structures (linked-lists, scoreboards, memories), directed, algorithmic, constrained random, and coverage driven random testing, and functional coverage.

VHDL Coding for Synthesis

Learn VHDL RTL (FPGA and ASIC) coding styles, methodologies, design techniques, problem solving techniques, and advanced language constructs to produce better, faster, and smaller logic.