Clock-Domain Crossing | Verification Academy

CDC Verification Sessions

A Methodology for Comprehensive CDC+RDC Analysis

This session will help you improve your development schedules and predictability by identifying the key functions and processes that must be deployed in a comprehensive CDC and RDC methodology.

Preventing Glitch Nightmares on CDC Paths: The Three Witches

In this paper, we first explain the glitch problems in various types of CDC paths. Then, we summarize the automatic formal-based glitch detection methodology [2] that we have deployed for a few years.

Advance your Designs with Advances in CDC and RDC

In this session you will gain an understanding of valuable new capabilities available in Questa CDC, RDC and Signoff CDC that are important to leverage early and often in development to ensure working and error-free multi-clock and reset designs.

A Methodology for Comprehensive CDC Analysis

In this session we will talk about the right methodology of Clock-Domain Crossing analysis for early design closure.

When Are You Done Running CDC?

In this session you will learn whether or not you might still have asynchronous clock or reset issues lurking in your design, despite having identified the crossings, ensured synchronizers are present, and reviewed your code – or even already run CDC analysis, ensuring that all CDCs are solid.

Questa® CDC Verification Demo

This session demonstrates the Questa® CDC Verification comprehensive solution to clock-domain verification.

Why Reset Domain Crossing Verification is an Emerging Requirement

In this session, you will learn what RDC covers that CDC does not and the appropriate time in the development cycle to deploy RDC.

Clock-Domain Crossing Analyses and Verification

This session explains the importance of a complete CDC methodology to produce error-free silicon.

Integrated Approach to Power Domain/Clock-Domain Crossing Checks

Power Aware/CDC simulations play an important role in System Resources block verification. The session discusses overcoming challenges in making the testbench work seamlessly across NON_PA and PA configurations.

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

In this session we will share a real world case study of how the customer applied Questa CDC the RTL level, then Questa Signoff CDC for gate-level CDC and glitch detection to wring out 3 glitches among millions of signals. (One of the glitch sources found was one that they had suspected; but the other two were a complete surprise.)

Clock-Domain Crossing with HDM - Enhanced Accuracy and Seamless Visibility at SOC Level

CDC Analysis at SOC level involves huge challenges in terms of capacity, quality of results, and ease of debug, dependencies and ownership of IPs. The flagship SOC designs are typically the biggest and the most complex.

Why Gate Level CDC is Needed (Even After RTL CDC Closure!)

In this session, you will learn how to leverage inputs from RTL CDC verification to automate and accelerate gate-level CDC verification closure with very "low noise" results.

My Experience with Questa® CDC Bring-Up

In this session, you will learn from Knowles Intelligent Audio on how they utilize Questa® CDC to achieve successful results.

What Is CDC Protocol Verification, Prevent Bugs in Your Silicon

What Is CDC Protocol Verification, and Why You Absolutely Need It To Prevent Bugs in Your Silicon Session | Subject Matter Expert - Kurt Takara | Academy Live Web Seminar

In this session, we discuss the pros and cons of various approaches to verifying CDC protocols and we show how Questa CDC automatically generates protocol assertions.

Orange is the New Black, Reset Verification is the New CDC

In this session we will show how to an automated formal app can exhaustively identify reset-specific killer bugs in your design.

Questa® CDC Power Aware Demo

This session demonstrates the Questa® CDC Power Aware solution for verifying low power designs including clock domain crossing (CDC) and voltage domain crossing (VDC) paths.

How to Keep UPF from Ruining Your CDC Analysis

In this session we will discuss the effects of advanced low power design on CDC by the addition of isolation cells, retention cells, level shifters, and dynamic voltage scaling.

Describing Low Power Logic with UPF

This session describes the clock-domain crossing requirements for low power designs and explains the CDC issues introduced by power control logic.

Integrating Power Aware CDC into a Design Flow

This session describes a low power verification methodology and how the Questa® Power Aware CDC solution may be integrated into your design flow.

Understanding Low Power Impact on CDC Logic

This session describes the impact of low power design techniques on design and CDC logic and also explains dynamic voltage and frequency scaling (DVFS) and its effect on CDC design and verification.

Power Aware CDC Introduction and Overview

Introduction and Overview Session | Subject Matter Expert - Kurt Takara | Power Aware CDC Verification Course

This session introduces the design challenges created by low power designs and the implications that these designs have on CDC verification.

Next-Generation Power Aware CDC Verification – What Have We Learned?

This paper describes what we've learned from next-generation Power Aware CDC verification including low power design challenges.

Questa® CDC Demo

Questa CDC addresses a number of critical verification issues that simply cannot be dealt with by simulation-based verification techniques.

Understanding Coverage Holes

This session will review the analysis of coverage results to identify and respond to coverage holes appropriately.

CDC Verification of an Accelerated Processing Unit

This session will show how formal technology solutions ease the verification of critical elements of your designs such as Clock-Domain Crossings and CDC synchronization logic.