Here's a collapsed set of questions asked during the live web seminar along with Chris's answers. If you don't see your question here, or need further clarification, you can always ask on the Verification Academy Forums.
Why we need to avoid `uvm_do macros?
The uvm_do macros were created to replace the 4 steps of create(), start_item(), randomize(), and finish_item(). They allow a new user to create and send a transaction in one step. However, they hide details too well, so if you want to perform something outside of these steps, you need to keep going back to the documentation, or pull apart the cryptic code in the macros. I recommend learning the 4 steps so you know what is really going on.
If I disable fork, does the sequence get killed?
A virtual sequence can start several child sequences in a fork-join* block. A "disable fork" can stop the sequence thread, but the sequencer that is negotiating with that sequencer will probably be left in a bad state. That will cause simulation errors, and there is no way to reset the sequencer. Instead, put a "done" flag in the sequence. When the virtual sequence sets the flag, the sequence should exit cleanly, leaving the sequencer in a good state.
What's is the best way to give configuration to sequence?
There are multiple ways to pass configuration information to a sequence. I covered several of these in the web seminar: UVM Coding Guidelines.
What should be used to configure layered sequences? 1.configdb. 2.p_sequencer. 3.m_sequencer
There are many ways to configure layered sequences, including the uvm_config_db. I described some techniques in my UVM Coding Guidelines web seminar. A sequence can find its context through the sequencer by calling get_sequencer(). This is a better coding style than m_sequencer, which is an internal variable.
Is there a "correct" way to access any design signals from sequences?
To be reusable, a sequence should never access a design signal directly, as that would tie it to a specific design configuration and signal names. I like the how UVM Framework does this: it makes methods in the configuration object. For example, wait for N clock cycles, and wait for reset to de-assert. If you are doing white box testing, sampling many internal design signals, use the bind construct as shown in https://verificationacademy.com/forums/systemverilog/how-connect-interface-internal-signals-module
Does sequence be a part of environment? If not , why isn't the sequence part of the environment?
A sequence should not be part of the environment. A sequence is stimulus, and is very test-specific. Every test may start a different sequence, or pick from a package of sequences. The sequences and virtual sequences may connect to multiple agents, but generally do not interact with the environment.
How to pass a virtual interface to a driver or monitor without using configuration data base?
I described some techniques in my UVM Coding Guidelines web seminar. The test class extracts the virtual interface from the uvm_config_db and puts it into a config object. It can then either pass a handle to that object down to lower components through a set_config() method in every component. Compared to the uvm_config_db, these set_config() methods are easier to understand and follow good programming practices.
Can we tweak a testbench that would work for block level and SoC?
This is an open ended question. A short answer, focusing just on sequences, is to create a base sequence class and a base sequence item class. Extend the classes to create new functionality. Remember, a sequence can be written with a base item class, then the test can do a set_type_override() to inject a derived flavor of transaction. Thus a sequence can produce different flavors of stimulus depending on what override is in place. There is a deep topic, more than I can answer in a few sentences.
In your book you explain about uvm lib or just systemverilog?
My book, SystemVerilog for Verification, was written before UVM. However, it discusses methodology concepts such as phases and sequences than are using in UVM.
Can you share an example of code for probing/forcing signals?
I suggest you look on web for this type of example. Verification Academy is one place to look, and here is a related posting: https://verificationacademy.com/forums/systemverilog/how-connect-interface-internal-signals-module.
