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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

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    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
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      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
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  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
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      • Register Abstraction Layer
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      • UVM Connect - SV-SystemC interoperability
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      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Featured & On-Demand

      • Continuous Integration - March 28th
      • Questa Verification IQ - April 11th
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      • 2022 Functional Verification Study
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      • Protocol and Memory Interface Verification
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    • On-Demand Library

      • Practical Flows for Continuous Integration
      • Lint vs Formal AutoCheck
      • The Three Pillars of Intent-Focused Insight
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      • HPC Protocols & Memories
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      • The Dog ate my RTL
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    • Siemens EDA Learning Center

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      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
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  • Protocol and Memory Interface Verification in the Shrinking World of 3DIC Subject Matter Expert

Protocol and Memory Interface Verification in the Shrinking World of 3DIC Subject Matter Expert

Gordon Allan

  • Introduction
  • Video
  • Subject Matter Expert
Other sessions in this seminar:
Gordon Allan -

Bio

Gordon Allan is the Questa Verification IP Product Manager at Siemens EDA. Gordon was one of the architects and developers of Accellera UVM, and was responsible for the UVM/OVM Methodology Cookbooks published on the Verification Academy website and appreciated by over 65,000 engineers worldwide, as well as several conference papers on Verification topics at DVCon and elsewhere. Prior to joining the EDA industry in 2010 he gained over 18 years of SoC Design and Verification experience in lead engineer and senior consultant roles, working with many of the top semiconductor companies, fabless startups, system houses and EDA companies worldwide and giving him firsthand experience of customers’ challenges from spec to tapeout. Gordon is based in Silicon Valley.

Featured Sessions
Verification of HPC Protocols and Memories Preparing for PCIe 6.0 - Part II - Verification of PCIe IP VIP Solutions for Protocol and Memory Verification Productivity in the Questa Simulation Flow Productive Low Power Debug Across All Engines and Flows Breaking the Speed Limits on SoC Verification SoC Verification with the Questa® Flow System Level Debug & Analysis Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy UVM Debug Made Easy – Map, Trace, Track, Find and Fix Bugs Improving UVM Testbench Debug Productivity and Visibility Evolution of Debug
Resources
UVM Cookbook Verification Horizons Blog The Evolution of Triage - Real-time Improvements in Debug Productivity The Big Brain Theory: Visualizing SoC Design & Verification Data Tried/Tested speedups for SW-driven SoC Simulation
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