SystemVerilog Assertions (SVA) are part of an IEEE standard defining a dedicated assertion language (IEEE P 1800 Standard). SVA leverages SystemVerilog operators and expression syntax for Boolean expressions. It adds temporal operators to describe the behavior and relationship of signals over time. This makes SVA a powerful tool that describs complex behavior for formal, simulation ,and emulation engines.
SystemVerilog Assertions are built from Boolean expressions, sequences, and properties. Properties are asserted with an assert, assume or cover statement. Assertion statements are combined into various constructs including modules, interfaces, and packages
More generally, an assertion is a statement of design intent that describes a behavior that a design should always, eventually, or never show. To view more information on Assertion Based Verification methodology check out the courses provided by Harry Foster here.
