Here's a collapsed set of questions asked during the live web seminar along with Chris's answers. If you don't see your question here, or need further clarification, you can always ask on the Verification Academy Forums.
What is the difference between a structure and an array?
All elements of an array are the same type, while a structure can contain elements of different types.
What is the difference between a structure and a class?
A structure just holds elements (data), while a class encapsulates both data and the routines that operate on the data. Class objects are dynamic.
What cannot be put into a package?
A structure can not contain nets or wires.
Why are routines in a package declared as automatic?
A routine in a package is shared by multiple modules and needs to be reentrant.
(When) would it make sense to move a module definition into a package as opposed to using a plain module within a regular SystemVerilog file? What are the advantages of preferring one over the other?
When you need to share a definition between modules, put it in a package. So if you have a class, structure, parameter, enum, typedef, routine used in more than one module, put it in a package.
What are some examples of Structure usage in UVM/Methodology based environment, when we use mostly class based entities?
UVM is 99% classes. The only structure you will see is uvm_reg_bus_op which holds information about a UVM register access, such as address, data, read/write, mask, etc.
How does an object works for the class?
A class is a definition, showing the variables and routines in the class, similar to the blueprint of a house. But, you can't live in a blueprint, you need to build a house. When you call the class constructor (the new() function), SystemVerilog instantiates the class by allocating space in memory for it. Just as you can build a neighborhood of houses from a single blueprint, you can construct many objects from a single class definition.
Do packages inside packages conflict with same type in another?
Try a small example for yourself. a_pkg has a definition for the parameter p=1. b_pkg imports a_pkg::*, and also defines a parameter p=2. Then import b_pkg::* in a module and $display(p). What do you see? When does SystemVerilog search a package that is wildcard imported?
Any special considerations for when the dut is written in VHDL (Testbench is in SystemVerilog and or UVM)?
Questa can share a SystemVerilog package with VHDL. In the Questa Sim User Guide, search for “mixedsvvh”, and review the example.
Can you explain why a package cannot be included in another module?
When you compile a package, a binary version is stored in the work library. When a module then imports the package, it reads this compact version, which is much faster, especially since the package is only searched when a definition is not found in the module. The UVM package is almost 70,000 lines of code, but importing the precompiled version is almost instantaeous. Including it during compilation would be much slower.
When should we use a structure as opposed to an object?
A structure only holds data, while a class encapsulates data and the routines that operate on the data. You can define hardware with static structures. A modern testbench needs Object Oriented Program, with dynamic classes. Both have their place in design and verification.
What is use of unions in design?
Packed unions are useful for accessing the same bits with different layouts. For example as an array of bytes versus an array of words.
module "name" import pkg::*; Is this synthesizable?
Yes. This is the best way to have module ports with abstract types, like instruction_t and structures.
Why can't you reference RGB_pkg::RED and traffic_pkg::RED instead of unqualifying the names?
You can, as shown in the video and slide deck. That style requires more typing, so you decide.
How is the package imported into the module?
You can wildcard import a package, or just import selected declarations.
Can you parameterize SystemVerilog packages and/or structs? If not, how do you deal with this in synthesizable code when parameterization is needed?
A parameter in a package can not be redefined later. A structure can be defined with parameters, which could be redefined later, unless the parameters were defined in a package.
Can you take an example and explain each concept by putting those things in testbench like some protocols PCIe or HBM interfaces etc.
This is a very open-ended request. Please provide a basic example and we can explore.
Why mask4_t has to be specifically imported and * did not work on the slide 'Package Layering'?
Declarations are only imported if they are used. The chip_pkg does not use mask4_t, so it does not import it, and so mask4_t is not exported. That is why it is not visible in the top module.
In package layering:
module top(…);
import bus_pkg::*; <-- this can help and resolve the issue mask4_t visiblity
import chip_pkg::*;
data32_tnew_data; // Visible?
mask4_t mask; // Not visible…
endmodule;"
There are multiple ways to solve the mask4_t problem in the package layering slide. You could explicitly import mask4_t in chip_pkg, make a dummy declaration with mask4_t in chip_pkg, import bus_pkg in the module top, or just import bus_pkg::mask4_t in module top.
