Driven by process technology needs, government legislation, and continued product integration and miniaturization, reducing power consumption is a mainstream and essential design requirement for many industry segments; including networking, mobile, automotive, consumer, and IoT. Because of this, many designs now employ sophisticated power management techniques. For example, design teams implement more power domains per design where each power domain can be placed in many different power states. Unfortunately though, most project managers lack a standard metric for power verification, and because of this do not know how well power management is verified Besides using power management techniques, design teams are also trying to reduce their power in the RTL design process by reducing unnecessary switching activity. This process can be difficult and the ultimate effect from RTL modifications are hard to predict. Lastly, to get a comprehensive methodology for both power measurement and power reduction, it is important to have realistic and accurate switching scenarios for particular power modes. Again, these can often be difficult to create and depend on very large datasets to drive verification results. In this tutorial, we will step through a complete low-power methodology, and explore the different types of metrics needed at different phases of the design process. It will cover a new and unique low-power coverage methodology that enables designers to verify and track how well they have tested their power management architecture. It will also show how to track not only metrics for how much power is used in the RTL, but also how much power is still being wasted and has potential to be reduced for IP qualification. Finally, it will step through how to bring real power scenarios testing into both your power measurement and management coverage metrics to provide the final phase of power verification and validation.
