As the complexity of SoC designs grows, it takes longer to do functional verification. Tests run way longer than they used to - a few hours to days - and there are thousands of them to run. It is not surprising to see a long-drawn out design verification cycle.
One of the common characteristics of functional verification of today’s complex designs is that they go through some sort of initial setup phase, whether it is design initialization, reset state, configuration phase, or sequence initialization. This initial setup phase is typically common for all the tests, or for a particular set of tests or a set of test configurations. In addition, this setup phase itself takes a substantially large amount of cycles with respect to overall length of the simulation for a test, and these cycles must be repeated over and over again for all subsequent tests.
This paper will discuss how to write the design so that the common initial setup phase simulation is done once and then used as a foundation to run different tests later on, including the ability to change test stimulus to simulate different test behaviors. We will also discuss what type of designs (Verilog, VHDL, SystemVerilog, UVM-based, SystemC, C/C++ models, PLI/FLI/VPI etc.) will fit in this methodology and what a designer can do to make his design fit for such methodology. Also covered: the constraints that need to be followed in order for this methodology to work, the design factors that might prevent a designer or verification teams from adopting this methodology (and how to overcome them).
We will also touch briefly upon the co-simulation verification environment (simulation-emulation) requirements and discuss how the same methodology would work with either simulation or co-simulation verification.
We will use examples from real world designs to show how this methodology can be used successfully, what changes are required to unblock some of the design factors, and elaborate on the potential gain and regression throughput that is possible.
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