This paper focuses on the process of verification of a System-on-a-Chip (SoC) consisting of multiple ARM® AMBA® AXI™ bus fabrics with mix of RTL IP and verification IP master and/or slave blocks. Specific focus in this paper is adjusting stimulus generation in order to maintain consistent bandwidth loads. Adjusting loads is done two ways - by adjusting the arrival rate, and adjusting the transaction delays.
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