Mixed-signal designs (such as multi-slope/ΔΣ ADCs, phase locked loops, high-speed I/O links, etc.) usually involve close interactions between analog and digital sub-circuits. However, digital blocks (such as digital filters, phase frequency detectors, frequency dividers or control logic) can consist of a large number of transistors – much larger than their analog counterparts. These digital circuits severely slow down the simulation, while simulation results may only capture unnecessarily accurate details of digital blocks. Since for digital circuits, an RTL representation, or even just a finite state machine model, can describe circuit behaviors well enough, it is preferable to use these high-level models during simulations of the whole system. In this session we describe how Mentor’s Symphony verification platform addresses the need of such mixed signal methodology and improve simulation throughput for faster TTM.
