Increasing usage of multi-clocking architecture to meet high performance and low power requirements of the modern SOCs makes clock-domain crossing (CDC) verification a critical step in design verification cycle. CDC verification is not only necessary on RTL; as the available "bandwidth" at the 28 nm nodes and below decreases, RTL-to-Gate synthesis can create glitches and CDC issues that are unobservable by CDC analysis at the RTL level that can lead to silicon failure. However, attempting CDC closure on gate-level designs with an RTL-level flow results in a very high setup effort, analysis scalability challenges, and an unwelcome volume of low quality, "high noise" results. In this presentation, we review the causes of these challenges and introduce an automated approach to overcome these difficulties. The proposed methodology is based on leveraging inputs from RTL CDC verification to automate and accelerate gate-level CDC verification closure with very "low noise" results.
