One of the biggest challenges for any chip design is to deliver a high-quality product, and at the same time, meet the project schedule. As projects iterate through debugging cycles, long turnaround time can become costly in terms of project schedule. This issue can be alleviated with a significant speed up in simulation. This is where emulation fits in. In our case, we mapped the design onto the Veloce emulator and made some modifications to the test bench environment, which is primarily UVM. This accelerated our overall verification process allowing us to run many more cycles using considerably more complex tests. In this session, we will look at the major issues encountered, lessons learned, and the final results of migrating a complex ASIC with a UVM-based environment to the Veloce emulator.
