The Mentor Veloce emulation platform combined with the Questa verification solution can run designs in RTL orders of magnitude faster than simulation alone. As a result, emulation is used to execute verification runs that would be otherwise impossible in logic simulation. Often these verification runs include some software executing on the design – as software is taking an increasing role in the functionality of a System-on-Chip (SoC). With significant software being executed in the context of the verification run, there needs to be some way to debug it. This session covers the various methods provided for debugging software in the context of emulation.
