=-=-=-=-= Keynote =-=-=-=-=
Title: Optimizing Time to Bug: Don’t Panic!
Abstract: We often hear the claim that “there is no silver bullet in verification.” But why is this true? Why do certain classes of design problems lend themselves better to one particular verification technique, but not another? This keynote will begin with a discussion on how to characterize FPGA and ASIC/IC complexity, and then identify appropriate verification solutions for specific classes of design problems, and finally quantitatively show their effectiveness.
=-=-=-=-= Formal Technical Talk =-=-=-=-=
Title: The Coming-of-Age of Formal Technology
Abstract: This talk explores today’s broad landscape of formal technology, where we find that formal has finally moved beyond the bounds of research and early adopters and now serves as a key and critical component of today’s functional verification process. In this session you will learn how Questa® Formal Verification tools can be easily integrated into a traditional simulation-based verification flow to yield higher quality results with reduced schedule.