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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Introduction to UVM
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      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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      • Coverage Forum
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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
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      • Occurrence Property Patterns
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    • Pattern Resources

      • Start Here - Patterns Library Overview
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      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
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      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Featured & On-Demand

      • VA Live - Multiple Dates & Locations
      • Interconnect Formal
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    • On-Demand Library

      • SystemVerilog Assertions
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      • Questa Verification IQ
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      • Protocol and Memory Interface Verification
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      • Preparing for PCIe 6.0: Parts I & II
      • High Defect Coverage
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      • Complex Safety Architectures
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      • Questa Lint & CDC
      • Hierarchical CDC+RDC
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • The Three Pillars of Intent-Focused Insight
      • All Webinar Topics
    • Conferences & WRG

      • 2022 Functional Verification Study
      • Improving Your SystemVerilog & UVM Skills
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      • DVCon 2023
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      • DVCon 2021
      • Osmosis 2022
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    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

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  • Low Power Verification Forum

Low Power Verification Forum

Reducing power consumption is a mainstream and essential design requirement for many industry segments; including networking, mobile, automotive, consumer, IoT and many others. Besides using power management techniques, design teams are also trying to reduce their power in the RTL design process by reducing unnecessary switching activity. This process can be difficult and the ultimate effect from RTL modifications are hard to predict. This forum will explore the new and unique low-power coverage methodologies that enable designers to verify and track how well they have tested their power management architecture. It will also show how to track not only metrics for how much power is used in the RTL, but also how much power is still being wasted and has potential to be reduced for IP qualification. Finally, it will step through how to bring real power scenarios into both your power measurement and management coverage metrics to provide the final phase of power verification and analysis.

During this seminar we have invited our valued partner and low power expert, Sriram Hariharan from Qualcomm. He will be address the low power challenges and trends he is seeing in the industry and what tools and methodologies are available to address them.


Gordon Allan
Sriram Hariharan
Qazi Faheem Ahmed
Shantanu Samant
Rick Koster
Acceleration Coverage Debug Simulation-Based Techniques
Walk

Sessions

Introduction and Overview

Low Power Verification Forum | Introduction and Overview | Gordan Allan

In this session, you will be introduced to new and unique low power coverage methodologies that enable designers to verify and track how well they have tested their power management architecture.

Industry Advancements Required to Close the Power Management Verification Gap

Industry Advancements Required to close the Power Management Verification Gap | Sriram Hariharan - Qualcomm, Inc.

In this session, you will learn how Qualcomm overcomes their Power Verification Challenges and how they utilize Power Aware Verification techniques.

Deploying A Metrics Driven Low Power Methodology for Your RTL IP

Deploying A Metrics Driven Low Power Methodology for Your RTL IP | Qazi Faheem Ahmed - Mentor, A Siemens Business

In this session, you will learn how PowerPro is a single solution for RTL Audit, Power Optimization, Estimation and Exploration.

Low Power Verification & Analysis with Emulation

Low Power Verification & Analysis with Emulation | Shantanu Samant - Mentor, A Siemens Business

In this session, you will learn how Emulation techniques can be used for Low Power Verification including Power Analysis and Power Estimation.

Low Power Considerations for Verification

Low Power Considerations for Verification | Rick Koster - Mentor, A Siemens Business

In this session, you will learn how to implement power reduction techniques and power management concepts.

Productive Low Power Debug Across All Engines and Flows

Productive Low Power Debug Across All Engines and Flows | Gordon Allan - Mentor, A Siemens Business

In this session, we will answer the top nine questions asked for debugging low power in your design.

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