Design IP has been one of the major enablers of innovation in new silicon designs. With the vast selection and specialization of IP today, and an increased focus on design IP development, silicon designs today can be completed within shorter design cycle times while meeting the power, performance and area metrics necessary to compete with other offerings. As a core part of the design, IP must be validated both by IP production and integration teams. Any issues that remain undetected will cause schedule delays down the road, and severe issues can potentially cause silicon failure or a sub-optimal final design. With more data to validate due to shrinking process technology nodes, and the need to source IP from different providers due to specialization, the costs and effort for IP validation has grown significantly. This session will show Solido Crosscheck as the one-stop-shop solution for IP validation and QA accountability among IP designers and IP integrators.