Wouldn't it be great if you could begin serious verification before a testbench was available? Even better, what if your verification process gave you exhaustive results? Formal verification delivers on both counts, and today automated formal-based applications enable anyone who knows RTL D&V to address high-value verification challenges in an intuitive, interactive manner. In this session, we will start by reviewing the unique capabilities in Siemens EDA's formal solutions, then share a case study on how automated formal "unreachability" analysis can accelerate overall verification coverage closure via integration with QuestaSim. Plus: if you already have some expertise in property checking, we will also share several apps that leverage this experience to address challenges like validating the completeness of your verification plan, processor/RISC-V verification, and FPGA implementation.
