Join Harry Foster, Tom Fitzpatrick and other Verification Academy experts to hear the latest updates on verification trends that are pushing the need for advanced verification.
Hear how users in the industry are adapting and taking a new look at verification methodologies to help build higher quality and more competitive on-time products in today’s evolving FPGA and ASIC markets. These sessions will discuss the most recent Wilson Survey on verification trends, the UVM Framework, a code base and generator used to implement verification infrastructure, interconnect, and operation. This includes writing constraints to characterize stimulus and configuration, creating prediction models, and defining coverage models with rapid testbench development utilizing the Questa Verification IP configurator to create high quality verification environments. In addition, learn about the ability of the Veloce platform for hardware-based acceleration and the full suite of Formal Apps and how they can be applied to a specific verification challenge in your organization.
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