Wouldn’t it be great if you could begin serious verification before a testbench was available? Even better, what if your verification process gave you exhaustive results? Formal verification delivers on both counts, and today new property creation and debug capabilities enable regular engineers to make use of classical formal techniques to explore their design’s behavior in an intuitive, interactive manner. Even without knowing a lot about assertions formal can be used to “smoke test” the design during development and explore various scenarios which may be challenging to verify at the chip level. Applying formal early shortens the overall verification cycle by finding and fixing most bugs during development instead of late in the verification game.
