Forum Search | Verification Academy

Results

SVA- To check value at previous OR current OR next clock cycle

Posted by John Pratheep on Jun 1, 2023
SystemVerilog SVA Assertion Systemverilog #System verilog Hi, when B asserted, A should be asserted at previous clock OR current clock OR next clock. How do we write better SVA assertion? assert property (@ (posedge clk) $rose (B) |-> ## [0: 2] $past ( ...

Question
SystemVerilog

SVA Assertion Systemverilog #System verilog
uvm1.2 "starting_phase = null" but sequence still working.

Posted by ekgren on Jun 1, 2023
UVM starting_phase Hi I just switched to uvm1.2. In my sequence task body there's: var uvm_phase starting_phase = get_starting_phase (); if (starting_phase!= null) begin... end else `uvm_error ("starting phase = null") During the simulation ...

Question
UVM

starting_phase
How to know on which sequence the current sequencer is running?

Posted by ravitejavoora on Jun 1, 2023
UVM One my sequencer/driver is getting started even though non of my sequences call it. I want to know from which sequence, the sequencer/driver is getting started. Is there a way to print/get the sequence information in sequencer? ...

Question
UVM
will always_comb block trigger if the signal value changes from 0/1 to X

Posted by sj1992 on Jun 1, 2023
SystemVerilog #System verilog force release always_comb Hi, Will always_comb block trigger if the signal value changes from 0 or 1 to X? I am trying to force a signal to 0 if it changes to X. Below is my code. Will this work? logic [2: 0] signal; always_c ...

Question
SystemVerilog

#System verilog force release always_comb
How to access a variable inside a UVM class and connect it to an SV interface?

Posted by gpb on Jun 1, 2023
UVM Class variables inside SV Interface I need to connect a variable present inside a uvm_component class to an interface. I tried using uvm_top to access the sign al and connect it but, it is not working. I need the class variables to be visible on the w ...

Question
UVM

Class variables inside SV Interface
Why p sequencer

Posted by Raja VA on Jun 1, 2023
UVM I have seen people suggesting try to avoid p sequencer but can anybody tell how can we run two agents without using p sequencer? ...

Question
UVM
Bind keyword in multiple instances

Posted by g1neela on Jun 1, 2023
SystemVerilog Hi Forum, When I tried to instantiate a TEST_TB which contains binding interface and DUT in a top TB multiple times, I am getting an error like Duplicate instance of bind found. module DUT (input clk, bit [7: 0] Addr, output bit [7: 0] Data) ...

Question
SystemVerilog
Coverage for the value difference between associative arrays

Posted by rraa on Jun 1, 2023
SystemVerilog #System verilog #coverage #associative_arrays Hello, I have 2 associative arrays int assoc_arr_1 [string]; int assoc_arr_2 [string]; the string index are same in the two arrays. I want to cover for each index in the arrays, the difference be ...

Question
SystemVerilog

#System verilog #coverage #associative_arrays
About UVM in order Comparator class

Posted by Harsha vardhan on Jun 1, 2023
UVM comparator UVM IN ORDER COMPARATOR compare convert Hi, I am studying about the UVM in order comparator class and how to use it in my existing scoreboard but I am not getting enough information about this can any one please provide the documents or lin ...

Question
UVM

comparator UVM IN ORDER COMPARATOR compare convert
Flexible interface that supports scaler or arrays

Posted by jnbkeller on Jun 1, 2023
SystemVerilog interface array type mismatch Hi all, Thanks in advance for any suggestions. I'm presenting a conceptual example showing how I'd like to make an interface re-usable when connecting to a DUT with different data types. I'm tryin ...

Question
SystemVerilog

interface array type mismatch

Pages

1
2
3
4
5
6
7
8
9
…
next →