Forum Search | Verification Academy

Results

Module cannot see defines defined in pkg, if this pkg is imported inside module. What is the reason for it?

Posted by EleneSajaia on Nov 10, 2022
SystemVerilog package inside module module Package If pkg is imported inside module, the code inside `ifdef is not parsed during compilation. when pkg is defined outside the module everything works fine. Do you know what can be reason for that? package pk ...

Question
SystemVerilog

package inside module module Package
How to avoid "Too few instance port connections" error?

Posted by nimitz_class on Mar 1, 2022
SystemVerilog Build in module module instance too few port connections module instantiation Hi, I'm cleaning the repo for a new project and I hit the " Too few instance port connections " error in my top module. These ports have been intent ...

Question
SystemVerilog

Build in module module instance too few port connections module instantiation
Module instantiation from within a for-gen block, value of input port is not updating

Posted by Kumar Saurabh on May 19, 2020
SystemVerilog #systemverilog generate block module Here's the code: module top; reg [1: 0] in; wire [1: 0] out; test # (.WIDTH (2)) a_inst (.in (2'b10),.out (out)); initial $display ("in[1]= %b", top.a_inst.GENBLOCK [1].ch.in); endmodu ...

Question
SystemVerilog

#systemverilog generate block module
Which tools support module ports of type event?

Posted by dhrogoff on Oct 31, 2019
SystemVerilog module port event Hi all. Just hit a weird issue yesterday. I was partitioning some monitor/error code into sub-modules. One of the signals was an error named event that signaled that an error had occurred. I added this as an output port of ...

Question
SystemVerilog

module port event
Properties encapsulation

Posted by hamza on Apr 10, 2019
OVM encapsulation Properties module interface Hello, can anyone please explain to me when we need to encapsulate properties inside a module and when we need to encapsulate them inside an interface? What are the differences between the two methods? Thank y ...

Question
OVM

encapsulation Properties module interface
Reference model

Posted by JH_Engineer on Nov 4, 2018
UVM module #uvm #systemverilog Hi Guys, I have a questions about Reference model, what does it mean? how we build and implement it? does it just like the design module?,do we actually build a module that implement the spec.? Please, refer me to articles o ...

Question
UVM

module #uvm #systemverilog
Reusable bind wrapper module

Posted by ilia on May 19, 2016
SystemVerilog bind module parameter Hi, I would like to create a reusable bind module which could be moved to the different hierarchies. More precisely, I mean, inside the bind module wrapper there are several SystemVerilog binds whose bind target scopes ...

Question
SystemVerilog

bind module parameter
Converting a module to/using a module in OVM?

Posted by jdubrow on Nov 20, 2015
OVM interface configuration module We have a SV module that I need to port over to OVM. What is a good resource for that? The module basically takes two interfaces and copies data from one to the other based on a config. ...

Question
OVM

interface configuration module