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RAL
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  1. uvm_config_db get method is failing when null is passed to seq.start() method

    Posted by Reuben on May 16, 2020
    UVM null uvm_config_db #(...)::get() RAL I'm studying RAL and I experienced this situation wherein the uvm_config_db get method is failing when I use null handle for the sequencer in the seq.start() method. The uvm_config_db get method is in the body ...

    Question
    UVM
    null uvm_config_db #(...)::get() RAL

  2. uvm ral

    Posted by raghunalla on May 11, 2020
    UVM RAL https://ibb.co/qxRMg51 https://ibb.co/4WPyQJc https://ibb.co/3f309qh HI, i have apb adopter class inside i am using extension field and when try to access field i am getting segmentation error... in the above i have attached image link can u help ...

    Question
    UVM
    RAL

  3. UVM_RAL: Why Predictor calling bus2reg function(Adapter) 2 times automatically??

    Posted by raja.kuraku on Mar 24, 2020
    UVM Mirrored values and desired values in UVM RAL RAL Hi, I am writing and reading from the register by using (write and read) methods in UVM Reg Model. Write and read is happening perfectly. And I am printing the values in Adapter. But when I am reading ...

    Question
    UVM
    Mirrored values and desired values in UVM RAL RAL

  4. Setting endianness for every uvm_reg

    Posted by Edison_yu on Apr 9, 2019
    UVM RAL Hi, Assume I can't change reg2bus of adapter, and I want to write in register in different endianness, how can I do? I have already try this.default_map = create_map("", 0, 4, UVM_LITTLE_ENDIAN,0), change on the fourth argument (UVM ...

    Question
    UVM
    RAL

  5. RAL:: get_reg_by_offset() method

    Posted by mitesh.patel on Nov 14, 2018
    UVM RAL #UVM #RAL Hi all, I am having question on get_reg_by_offset() method of reg_map. As per the code, it has two arguments, one is offset which should be the address of the register [with additional base offset] for which register handle is needed, an ...

    Question
    UVM
    RAL #UVM #RAL

  6. [RAL] Problems with Memory Frontdoor Write

    Posted by sheila_hsu on Sep 11, 2018
    UVM RAL frontdoor memory Hi all, I'm trying to configure and verify my DUT via RAL. First, I write certain values to registers(or memory) through frontdoor access. Next, I read it through backdoor access and compare those values with the expected val ...

    Question
    UVM
    RAL frontdoor memory

  7. uvm_mem access

    Posted by saraTel on Aug 27, 2018
    UVM RAL mem UVM Hi, What is the command to get values from the addresses in the memory(in RAL), such as the use of GET in the registers. ...

    Question
    UVM
    RAL mem UVM

  8. one register map for multiple agents?

    Posted by soloist_huaxin on Jun 28, 2018
    UVM uvm_reg_map register adapter RAL so my design have a register layer that can be accessed from two different interfaces of the DUT. The address mapping is identical for both interfaces. Each interface has an agent for it, and the agent contains an adap ...

    Question
    UVM
    uvm_reg_map register adapter RAL

  9. UVM Register layer writing/reading X values

    Posted by SilentB on Jun 19, 2018
    UVM UVM RAL register layer x value Hi everyone, I have and UVM Register layer implemented in my UVM environment for BACKDOOR access to my logic signals and memories in RTL. But I have a problem with writing and reading X values. When I try to do those ope ...

    Question
    UVM
    UVM RAL register layer x value

  10. UVM_REG_BLOCK from UVM_REG

    Posted by nikhilverif on May 21, 2018
    UVM UVM uvm_reg RAL I want a handle of uvm_reg_block in uvm_reg as I want to write some different register from this reg_block. I am providing the exact scenario below. Reg_block and Register declaration: class ral_reg_1 extends override_reg; uvm_reg_fiel ...

    Question
    UVM
    UVM uvm_reg RAL

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