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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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Ask a Question
UVM #sequence
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  1. How to mask the write data and read data in a register in UVM sequence

    Posted by Harsha vardhan on Feb 21, 2023
    UVM #sequence #registers access register in uvm monitor #registers_testing register masking Hi, I want to mask the write and read data for a register in a sequence Example: I have a control register (ctrl_reg) with width of 32- bits The control register h ...

    Question
    UVM
    #sequence #registers access register in uvm monitor #registers_testing register masking

  2. Error on sequencer- send_request failed to cast sequence item

    Posted by Jose_Iuri on Feb 1, 2023
    UVM #uvm #sequence uvm_fatal casting I build a uvm testbench using RAL to understand the concept of the abstraction layer, but when i run the simulation i have a UVM_FATAL at my sequencer. Quote: UVM_FATAL @ 10: uvm_test_top.m_env.m_agent.m_seqr [m_seqr] ...

    Question
    UVM
    #uvm #sequence uvm_fatal casting

  3. Issue when using uvm_reg update method: "Accessing non-static members of a null object is not allowed"

    Posted by flo_gwt on Jan 26, 2023
    UVM #uvm_reg #sequence Hi, Running ubm_tb_build_bl_tb example on SPI interface provided in cookbook code examples (https://verificationacademy.com/cookbook/download?file=https://s3.amazonaws.com/courses.verification.academy/Uvm_tb_build_bl_tb.tgz&down ...

    Question
    UVM
    #uvm_reg #sequence

  4. How can one write a UVM sequence for cache eviction? Lets suppose main memory is 4GB. 64KB Cache, 4 way associative, 64B cache line. Any ideas would be appreciated

    Posted by rohandbz on Jan 13, 2023
    UVM #systemverilog #sequence #delay uvm_components I am thinking of writing something like this class seq extends uvm_sequence#(block_data); `uvm_object_utils(seq) function new(string name ="seq"); super.new(name); endfunction task body(); block ...

    Question
    UVM
    #systemverilog #sequence #delay uvm_components

  5. What is the use of sequence overrides.

    Posted by chetan_s on Oct 14, 2022
    UVM #sequence #override +uvm_set_inst_override set_type_override I'm going through the sequence override and here is the snippet code. In the snippet code in run_phase we are starting 3 sequences which actually runs the same sequence sequentially. My ...

    Question
    UVM
    #sequence #override +uvm_set_inst_override set_type_override

  6. how sequences is start?

    Posted by Vrajesh_Rojivadiya on Jun 26, 2022
    UVM #sequence #uvm #sequence #test how sequences is start? what is difference between sequence_handle.start (sequencer_handle) and `uvm_do_on (sequence_handle, sequencer_handle)? is it same? I have seen two virtual sequence example one of the example ther ...

    Question
    UVM
    #sequence #uvm #sequence #test

  7. uvm sequence for registers test

    Posted by abdelaali_21 on Jun 20, 2022
    UVM regmodel #sequence Hey all, I hope you're doing great. Im trying o verify my DUT registers, I add a regmodel in the TB. I wanted to make sure if some of my readings are correct or not. to test rw register access; Are uvm_reg_bit_bash_seq and uvm_ ...

    Question
    UVM
    regmodel #sequence

  8. UVM Constrains inside a sequence are ignored

    Posted by HelenLG on Jun 13, 2022
    UVM #constraint #randomization #sequence item #sequence #systemverilog #UVM Hi there, I am facing some issues trying to create some sequences, the constrains I added are not taken in consideration when the item is randomize. Do you have any idea why? clas ...

    Question
    UVM
    #constraint #randomization #sequence item #sequence #systemverilog #UVM

  9. Reactive agent for memory storage

    Posted by UVM_SV_101 on Mar 18, 2022
    UVM #uvm #reactive agent #sequence Hi, I have designed an reactive slave as memory storage component. It simple stores data at specified addr with write and read commands. Since I am running the sequence in forever loop. How do I end the simulation? class ...

    Question
    UVM
    #uvm #reactive agent #sequence

  10. get_response function in sequence does not get unblocked after put_response

    Posted by sj1992 on Feb 3, 2022
    UVM #systemverilog #UVM #sequence get_response #driver Hi, I have a sequence through which I send a request and expect a response back from the driver. I do see that the driver is putting the response using the put_response function, but I don't see ...

    Question
    UVM
    #systemverilog #UVM #sequence get_response #driver

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