Posted by Rahulkumar on Jun 24, 2019
SystemVerilog Hi, I want to generate the 7 consecutive ones in the 32bit variable. Constraint C1,(C21,C22) are working but C3,(C41,C42) aren't working.Why C3,(C41,C42) aren't working? Please can you explain it? class Ctrans; rand bit [31: 0] dat ...
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