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Multi instance agent

Posted by rag123 on Feb 28, 2023
UVM #uvm Hi, I have a uvm agent which was working completely fine for 1 instance. I am now doing multi agent and it seems its its failing when launching transactions on both the instances. It seems the basic test is hanging and i get assertion failure. He ...

Question
UVM

#uvm
UVM Verbosity settings for sequence/objects

Posted by rag123 on Feb 14, 2023
UVM #uvm Hi, Is there anyway i can use the UVM_verbosity settings to control messages on uvm sequences or uvm_object? I understand that it is for components. But wondering if there is any other way we can use it instead of turning on and off using +UVM_VE ...

Question
UVM

#uvm
Error on sequencer- send_request failed to cast sequence item

Posted by Jose_Iuri on Feb 1, 2023
UVM #uvm #sequence uvm_fatal casting I build a uvm testbench using RAL to understand the concept of the abstraction layer, but when i run the simulation i have a UVM_FATAL at my sequencer. Quote: UVM_FATAL @ 10: uvm_test_top.m_env.m_agent.m_seqr [m_seqr] ...

Question
UVM

#uvm #sequence uvm_fatal casting
APB write bin not getting hit

Posted by rag123 on Jun 22, 2022
UVM #uvm I am sampling a coverpoint based on Psel, but it looks like the Read bin and Read after Read gets hit. But for some reason i dont see the write bin getting hit. Here is the sample code. I see in the waves write access are going through. covergrou ...

Question
UVM

#uvm
Reactive agent for memory storage

Posted by UVM_SV_101 on Mar 18, 2022
UVM #uvm #reactive agent #sequence Hi, I have designed an reactive slave as memory storage component. It simple stores data at specified addr with write and read commands. Since I am running the sequence in forever loop. How do I end the simulation? class ...

Question
UVM

#uvm #reactive agent #sequence
Unable to compile a register model using registers of size 2048 bits

Posted by Marc43 on Mar 17, 2022
UVM UVM Questa questasim #uvm uvm register model Hello, I am unable to compile my register model using registers of size 2048 bits. I know that the default size is 64 and we have to do +define+UVM_REG_DATA_WIDTH=2048 when compiling UVM. But it doesn' ...

Question
UVM

UVM Questa questasim #uvm uvm register model
How to display time in femtoseconds for uvm_info statements

Posted by sj1992 on Mar 11, 2022
UVM #uvm UVM_VERBOSITY timescale uvm_info Hi, Is there is command-line option to display time in femtoseconds for uvm_info statements? At present all the uvm statements are printed out in nanoseconds Thanks ...

Question
UVM

#uvm UVM_VERBOSITY timescale uvm_info
Facing Issue with Parameter override from top_tb.

Posted by Pavan Kumar Kollipara on Feb 16, 2022
UVM #UVM #scoreboard #uvm #override #parameter Hello All, I am having query related to the parameter override. DUT: module dut (parameter A = 30, `include parameter_file.sv parameter B = 20) (// DUT ports) // code endmodule parameter file: parameter_file. ...

Question
UVM

#UVM #scoreboard #uvm #override #parameter
how to connect scoreboard with more than one monitor

Posted by Manirama on Feb 6, 2022
UVM #uvm #monitor #UVM #scoreboard hi everybody, In my env class, there is a master agent and slave agent. and i want to connect master agent monitor and slave agent monitor to scoreboard. The query i am having is: 1. do i need to create two scoreboard fo ...

Question
UVM

#uvm #monitor #UVM #scoreboard
Reading enum from a file

Posted by rag123 on Jan 15, 2022
UVM #uvm Hi, I am trying to read a enum from a file, but i dont see that is being driven from Sequence to driver and in the print statements. The example has read.txt which has 2 enum's and reading it from seq_a. Appreciate the help. Enum_from_file ...

Question
UVM

#uvm

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