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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
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      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
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      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
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      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • The Digital Twin: An Aerospace and Defense Revolution - March 9th
      • VIP solutions for Protocol and Memory Verification  - March 11th
      • Advance your Designs with Advances in CDC and RDC - March 23rd
      • Webinar Calendar

    • On Demand Seminars

      • The ABC of Formal Verification
      • I'm Excited About Formal...
      • 2020 Functional Verification Study
      • All On-Demand Seminars

    • Recording Archive

      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • All Recordings

    • Conferences

      • DVCon 2020
      • DAC 2019
      • All Conferences

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Academy Newsletter
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Verification Horizons - March 2020
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • Questa® inFact
      • Functional Verification Library
Ask a Question
#uvm
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  1. Multiple lock() in parallel sequences is broken in uvm-1.2?

    Posted by mitesh.patel on Mar 2, 2020
    UVM #uvm Cookbook: Sequences/LockGrab Hi All, We were exploring lock/grab feature of uvm_sequencer on UVM-1.2 using below code: class instruction extends uvm_sequence_item; typedef enum {PUSH_A, PUSH_B, ADD, SUB, MUL, DIV, POP_C} inst_t; rand inst_t inst; ...

    Question
    UVM
    #uvm Cookbook: Sequences/LockGrab

  2. Does UVM contains any program block?

    Posted by mitesh.patel on Jul 31, 2019
    UVM #uvm #systemverilog program program block Hi all, we were analyzing UVM library and have following question. As per our understanding, system verilog testcase is recommended to write inside program block or entire class hierarchy should be start/invok ...

    Question
    UVM
    #uvm #systemverilog program program block

  3. RAL:: Does mirrored and desired both values are needed for prediction of register?

    Posted by mitesh.patel on Jun 6, 2019
    UVM #UVM #RAL #uvm Hi, While doing RAL classes study, i am confused with mirrored and desired value. I came to know that desired means "what we want to design have" and mirrored means "what we think to design have". This statement is b ...

    Question
    UVM
    #UVM #RAL #uvm

  4. RAL:: Individual field access is working correctly?

    Posted by mitesh.patel on May 23, 2019
    UVM #UVM #RAL #uvm Hi all, While doing the RAL classes analysis, i came to know that there is "m_individually_accessible" field for each register field which can be set using configure() method. Here, as per my understanding, if this field is se ...

    Question
    UVM
    #UVM #RAL #uvm

  5. UVM Overriding: is it possible to revert existing overriding?

    Posted by mitesh.patel on May 20, 2019
    UVM #uvm factory overriding at run time Hi All, I have very strange requirement, where i have following base class. class base_monitor extends uvm_monitor;...   virtual function xyz_operation (); // Logic 1 is performed endfunction: xyz_operation... endcl ...

    Question
    UVM
    #uvm factory overriding at run time

  6. RAL:: What is uvm_reg_fifo?

    Posted by mitesh.patel on May 3, 2019
    UVM #uvm #UVM #RAL Hi While understanding the RAL classes, i came to know the uvm_reg_fifo also there, which is extended from uvm_reg. I gone through the implementation and I have following queries on the same. 1. In which application this can be used? 2. ...

    Question
    UVM
    #uvm #UVM #RAL

  7. Execution of connect phase twice in simulation

    Posted by mitesh.patel on Apr 8, 2019
    UVM #uvm UVM phases phase jump Hi All, I have one scenario, on which i want to change connections of analysis port run time. so,i thought to use uvm phase jumping, i know this is not as per the guideline, but i have too. So, my question is, if i jump to c ...

    Question
    UVM
    #uvm UVM phases phase jump

  8. RAL:: Run time disable

    Posted by mitesh.patel on Dec 5, 2018
    UVM #UVM #RAL #uvm Hi, I have following questions related to UVM RAL. 1. Is there any specific support to disable/delete reg or mem? once ral model is locked. 2. Can i change reset value run time? 3. What is the difference between explicate predictor and ...

    Question
    UVM
    #UVM #RAL #uvm

  9. RAL:: uvm_reg vs uvm_mem

    Posted by mitesh.patel on Sep 1, 2018
    UVM #UVM #RAL #uvm Hi, UVM RAL supports both uvm_reg and uvm_mem for registers and memories. can anyone explain what is the difference between uvm_reg and uvm_mem? I know about configuring uvm_reg, can any share code for configuring uvm_mem? How it is dif ...

    Question
    UVM
    #UVM #RAL #uvm

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