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Expression on rhs is not a class or a compatible class and hence cannot be assigned to a class handle on lhs.

Posted by morslai on Nov 17, 2021
UVM #uvm #systemverilog #sequencer Hello everyone, I am trying to assign the sequencer from my agent to the sequencer in the environment and I get the next error: Expression on rhs is not a class or a compatible class and hence cannot be assigned to a cla ...

Question
UVM

#uvm #systemverilog #sequencer
What is std_logic_vector16(15 downto 0)?

Posted by bstephen on Nov 16, 2021
UVM VHDL #uvm #systemverilog I came across a VHDL DUT with two data types that I am unfamiliar with:: in std_logic_vector16 (15 downto 0);: in std_logic_vector32 (31 downto 0); Can someone explain what these data types are? Also, can std_logic_vector16 an ...

Question
UVM

VHDL #uvm #systemverilog
solver fails to solve easy constraints

Posted by nimrodw on Sep 2, 2021
UVM #constraint #randomization #uvm #systemverilog #queues Here are the constraints the solver is unable to solve int int_q [$] = {0, 1, 2}; rand int q_size; rand int rand_int_q [$]; constraint easy_constraint_c {q_size inside {[3: 666]}; rand_int_q. si ...

Question
UVM

#constraint #randomization #uvm #systemverilog #queues
Strategy to monitor single signals

Posted by mago1991 on Jul 11, 2021
UVM #uvm #systemverilog UVM monitor Hi, Let`s say we have some interrupt signal that changes without any rules (no protocol). This signal should be compared with the reference signal in the SB. What is the correct way to monitor it? 1. every clock? using ...

Question
UVM

#uvm #systemverilog UVM monitor
Which region does Testbench use to drive the signal to DUT?

Posted by possible on Dec 14, 2020
UVM timing regions timing control #systemverilog #uvm Suppose, I have a clocking block in the interface(let's say vif) that I am using to connect the testbench to the DUT. I am using the clocking block to drive(vif.cb.var <= XX) and sample the DUT ...

Question
UVM

timing regions timing control #systemverilog #uvm
Ways to reduce simulation time?

Posted by possible on Dec 3, 2020
UVM #uvm #systemverilog simulation How can we reduce simulation time, in general? You can list out things like- 1) Writing better constraints, for example, whatever can be done in post_randomize(), avoid it in do via constraints. ...

Question
UVM

#uvm #systemverilog simulation
Interview Questions on UVM

Posted by Subbi Reddy on Nov 26, 2020
UVM #uvm #systemverilog I faced conflict to answer for the below Queries in interview,Please give knowledge in the below listed Queries: 1. don’t want to register a sequence to sequencer. What is the alternate macro to uvm_sequence_utils() macro? 2. For d ...

Question
UVM

#uvm #systemverilog
How driver will request each time to sequencer or sequence need different sequence_item on same interface

Posted by Subbi Reddy on Nov 26, 2020
UVM #uvm #systemverilog How driver will request each time to sequencer or sequence need different sequence_item on same interface ...

Question
UVM

#uvm #systemverilog
Multiple `ifndef requirement

Posted by xfinity on Oct 29, 2020
UVM #uvm #systemverilog Hello, I have requirement where a certain piece of code must not be executed: `ifndef BRIDGE and TOP $display ("Don't execute this "); `endif This gives compile error: I can do this `define BRIDGEandTOP and then ...

Question
UVM

#uvm #systemverilog
Test case fail

Posted by Subbi Reddy on Oct 11, 2020
UVM #systemverilog #uvm seed concept: Ex: I ran single test 9 times passing out of 10 times and one time is failing. Please help me, How to overcome from this issue ...

Question
UVM

#systemverilog #uvm

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