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Interview Questions on Assertions

Posted by Subbi Reddy on Nov 13, 2022
SystemVerilog #systemverilog #uvm Please give me solution the below listed Queries: 1. sig_a and sig_b are environment signals, which can be given at any time, but should never be given together 2. Every sig_a must eventually be acknowledged by sig_b, unl ...

Question
SystemVerilog

#systemverilog #uvm
Expression on rhs is not a class or a compatible class and hence cannot be assigned to a class handle on lhs.

Posted by morslai on Nov 17, 2021
UVM #uvm #systemverilog #sequencer Hello everyone, I am trying to assign the sequencer from my agent to the sequencer in the environment and I get the next error: Expression on rhs is not a class or a compatible class and hence cannot be assigned to a cla ...

Question
UVM

#uvm #systemverilog #sequencer
What is std_logic_vector16(15 downto 0)?

Posted by bstephen on Nov 16, 2021
UVM VHDL #uvm #systemverilog I came across a VHDL DUT with two data types that I am unfamiliar with:: in std_logic_vector16 (15 downto 0);: in std_logic_vector32 (31 downto 0); Can someone explain what these data types are? Also, can std_logic_vector16 an ...

Question
UVM

VHDL #uvm #systemverilog
solver fails to solve easy constraints

Posted by nimrodw on Sep 2, 2021
UVM #constraint #randomization #uvm #systemverilog #queues Here are the constraints the solver is unable to solve int int_q [$] = {0, 1, 2}; rand int q_size; rand int rand_int_q [$]; constraint easy_constraint_c {q_size inside {[3: 666]}; rand_int_q. si ...

Question
UVM

#constraint #randomization #uvm #systemverilog #queues
Syntax error: token is #

Posted by rishikpillai90 on Jul 14, 2021
SystemVerilog #systemverilog #uvm Hi, The following code of a file gives syntax error in VCS for typedef line. The message displayed is: Quote: Error-[SE] Syntax error Following verilog source has syntax error: FILENAME, LINENUMBER: token is # typedef bas ...

Question
SystemVerilog

#systemverilog #uvm
Strategy to monitor single signals

Posted by mago1991 on Jul 11, 2021
UVM #uvm #systemverilog UVM monitor Hi, Let`s say we have some interrupt signal that changes without any rules (no protocol). This signal should be compared with the reference signal in the SB. What is the correct way to monitor it? 1. every clock? using ...

Question
UVM

#uvm #systemverilog UVM monitor
Problem with Macro

Posted by possible on Jul 5, 2021
SystemVerilog macros and defines #systemverilog #uvm #constraint #randomization Hi, I'm seeing an issue with the following macro definition. Please help- `define random_f16 (COMP) \ sign_f16 dist {0:= 1, 1:= 1}; \ exponent_f16 dist {'hFF:/ 5, &# ...

Question
SystemVerilog

macros and defines #systemverilog #uvm #constraint #randomization
Guidelines for using analysis port in monitor

Posted by bhupeshpaliwal on Jun 29, 2021
SystemVerilog #systemverilog #uvm UVM monitor analysis port In reference to analysis port used in system verilog or UVM monitor, is there any specific guidelines on number of analysis port to be used? While I understand from SV LRM perspective there is no ...

Question
SystemVerilog

#systemverilog #uvm UVM monitor analysis port
Delay in signals at clocking block hierarchy w.r.t RTL hierarchy in waveform

Posted by GC on Mar 28, 2021
SystemVerilog #uvm #clockingblock Clocking Block #systemverilog input output skew There is a testbench env and I am working on some tests, I noticed that in the waveform if I pull a specific signal which is input to rtl from rtl hierarchy and pull the sam ...

Question
SystemVerilog

#uvm #clockingblock Clocking Block #systemverilog input output skew
How interaction happens between bins with different coverpoints without help of cross coverage

Posted by Subbi Reddy on Mar 23, 2021
Coverage #systemverilog #uvm #coverage How interaction happens between bins with different coverpoints without help of cross coverage Ex coverpoint covpt1 bins avar1; bins avar2; coverpoint covpt2 bins bvar1; bins bvar2; without using cross coverage needs ...

Question
Coverage

#systemverilog #uvm #coverage

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