Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • The Digital Twin: An Aerospace and Defense Revolution - March 9th
      • VIP solutions for Protocol and Memory Verification  - March 11th
      • Advance your Designs with Advances in CDC and RDC - March 23rd
      • Webinar Calendar

    • On Demand Seminars

      • The ABC of Formal Verification
      • I'm Excited About Formal...
      • 2020 Functional Verification Study
      • All On-Demand Seminars

    • Recording Archive

      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • All Recordings

    • Conferences

      • DVCon 2020
      • DAC 2019
      • All Conferences

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Academy Newsletter
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Verification Horizons - March 2020
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • Questa® inFact
      • Functional Verification Library
Ask a Question
uvm uvm_config_db
  • Home
  • Forums
  • Search

Forum Search

Results

  1. uvm_config_db get usage

    Posted by Pavan Acharya G on Aug 10, 2020
    UVM #uvm uvm uvm_config_db Hi, Can the cfg be set in the lower hierarchy and get at hierarchy? For ex: //check_env.sv (build phase) uvm_config_db#(cfg_check)::set(uvm_root::get(), "*", "cfg_h", cfg_h); //check_test.sv (build phase) uvm ...

    Question
    UVM
    #uvm uvm uvm_config_db

  2. how can i do "get" at two different paths with same key.

    Posted by tarugupt on Mar 27, 2020
    UVM set uvm uvm_config_db hi, i am having two instances of a file say A so A1 and A2 are two objects that are created. now i do set of a variable in a file say B for both the instances A1 and A2. i use uvm_config_db, do the set with same key, but to diffe ...

    Question
    UVM
    set uvm uvm_config_db

  3. Is it possible to pass a dynamic array through uvm_config_db#(...)::set/get

    Posted by Michael54 on Dec 15, 2019
    UVM uvm uvm_config_db Hi, I looking for a syntax or code example which is passing a dynamic array/queue using the uvm_config_db. For example, in my "generator component", I create different kinds of packets to be sent into my DUT. When one of th ...

    Question
    UVM
    uvm uvm_config_db

  4. How to set uvm_config_db for multiple instances.?

    Posted by Aparna Elango on Dec 10, 2019
    UVM uvm_config_db multiple interface uvm uvm_config_db Hello, I am following this link for creating an uvm_config_db set method https://verificationacademy.com/forums/uvm/issue-putting-array-interface-uvmconfigdb Code: parameter int myparams[4] = '{0 ...

    Question
    UVM
    uvm_config_db multiple interface uvm uvm_config_db

  5. Passing interface directly to driver in UVM?

    Posted by Sv-hustler on Sep 4, 2019
    UVM uvm uvm_config_db #uvm #factory How to pass interface directly to driver without sending them through config_db from top? ...

    Question
    UVM
    uvm uvm_config_db #uvm #factory

  6. Why uvm_config_db needs m_rsc?

    Posted by eda2k4 on Sep 24, 2018
    UVM uvm uvm_config_db Even though uvm_config_db extended from uvm_resource_db, it is mostly built on top of uvm_resource_pool directly. I'm confused about one data member in uvm_config_db, m_rsc. It is declared as a uvm_pool. static uvm_pool # (strin ...

    Question
    UVM
    uvm uvm_config_db

  7. A Better Way For Accessing And Maintaining Configs At Multi-Level Environment?

    Posted by desperadorocks on Sep 15, 2018
    UVM UVM uvm uvm_config_db Hello All, Have a scenario where I wanted to create muti-level environment and wanted a cleaner/better way of sharing the configs using the uvm_config_db. a. Say have a top level environment eatable_env and a top level environmen ...

    Question
    UVM
    UVM uvm uvm_config_db

  8. uvm_confg_db

    Posted by jayeshranjan on Apr 28, 2017
    UVM uvm_config_db #(...)::get() uvm uvm_config_db How to set a integer variable from test using uvm_confg_db method, which i can access in base class of default sequence in the environment. ...

    Question
    UVM
    uvm_config_db #(...)::get() uvm uvm_config_db

  9. The effect on the simulation performance in case using set and get uvm_config_db for individual values.

    Posted by saritr on Jan 11, 2017
    UVM uvm uvm_config_db I configure the following in the test file: uvm_config_db # (int):: set (uvm_root:: get (), "*", "data_xi_min", 5); uvm_config_db # (int):: set (uvm_root:: get (), "*", "data_xi_max", 12); And ...

    Question
    UVM
    uvm uvm_config_db

  10. Receiving DUT internal signals into test through uvm_config_db

    Posted by Jeevan Garlapati on Apr 28, 2015
    UVM uvm uvm uvm_config_db Hi I am facing an issue with uvm_config_db and need a clarification regarding the same. I have a requirement of probing the RTL and checking few signals in my test. I have assigned the signals to a tb bit and sent the bit using u ...

    Question
    UVM
    uvm uvm uvm_config_db

Pages

  • 1
  • 2
  • next →

Filter by forum:

  • UVM (11) Apply UVM filter

Filter by content type:

  • Question Remove Question filter

Filter by solution status

  • Has a solution (2) Apply Has a solution filter

Filter by author:

  • Aparna Elango (1) Apply Aparna Elango filter
  • desperadorocks (1) Apply desperadorocks filter
  • eda2k4 (1) Apply eda2k4 filter
  • jayeshranjan (1) Apply jayeshranjan filter
  • Jeevan Garlapati (1) Apply Jeevan Garlapati filter
  • Michael54 (1) Apply Michael54 filter
  • Pavan Acharya G (1) Apply Pavan Acharya G filter
  • ranjith palavarapu (1) Apply ranjith palavarapu filter
  • saritr (1) Apply saritr filter
  • Sv-hustler (1) Apply Sv-hustler filter
  • tarugupt (1) Apply tarugupt filter

Filter by question keywords:

  • uvm uvm_config_db Remove uvm uvm_config_db filter
  • #uvm (1) Apply #uvm filter
  • #uvm #factory (1) Apply #uvm #factory filter
  • multiple interface (1) Apply multiple interface filter
  • set (1) Apply set filter
  • uvm (1) Apply uvm filter
  • UVM (1) Apply UVM filter
  • uvm_config_db (1) Apply uvm_config_db filter
  • uvm_config_db #(...)::get() (1) Apply uvm_config_db #(...)::get() filter
Siemens Digital Industries Software

Siemens Digital Industries Software

##TodayMeetsTomorrow

Solutions

  • Cloud
  • Mendix
  • Siemens EDA
  • MindSphere
  • Siemens PLM
  • View all portfolio

Explore

  • Digital Journeys
  • Community
  • Blog
  • Online Store

Siemens

  • About Us
  • Careers
  • Events
  • News and Press
  • Newsletter
  • Customer Stories

Contact Us

USA:

phone-office +1 800 547 3000

See our Worldwide Directory

  • Contact Us
  • Support Center
  • Give us Feedback
©2021 Siemens Digital Industries Software. All Rights Reserved.
Terms of Use Privacy Cookie Policy