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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
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      • FPGA Verification
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    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
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      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
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      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • The Digital Twin: An Aerospace and Defense Revolution - March 9th
      • VIP solutions for Protocol and Memory Verification  - March 11th
      • Advance your Designs with Advances in CDC and RDC - March 23rd
      • Webinar Calendar

    • On Demand Seminars

      • The ABC of Formal Verification
      • I'm Excited About Formal...
      • 2020 Functional Verification Study
      • All On-Demand Seminars

    • Recording Archive

      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • All Recordings

    • Conferences

      • DVCon 2020
      • DAC 2019
      • All Conferences

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
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    • Verification Horizons Publication

      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Verification Horizons - March 2020
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
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    • Training

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      • Questa® inFact
      • Functional Verification Library
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  1. I want to write an assertion for checking that the data stable for 16 clock cycles and continue the checking for the next 16 cycles and so on.?How can i write this?

    Posted by adharshh on May 7, 2020
    UVM SVA $stable Hi, i am very much new to the topic and need help in understanding I am writing an assertion where as long as tx_frame is high, it should check the data stable for 16 cycles. i wrote something like this, but its not happening as needed. a1 ...

    Question
    UVM
    SVA $stable

  2. Re: I want to write an assertion for checking that the data stable for 16 clock cycles and continue the checking for the next 16 cycles and so on.?How can i write this?

    Posted by adharshh on May 7, 2020
    In reply to ledzep_1988: Uart data bit may or maynot change after 16 baud cycles. i dont think the above assertion could meet the requirement. Thankyou. ...

    Reply
    UVM
    SVA $stable

  3. Re: I want to write an assertion for checking that the data stable for 16 clock cycles and continue the checking for the next 16 cycles and so on.?How can i write this?

    Posted by adharshh on Apr 30, 2020
    In reply to chr_sue: I am not sure why, but the above one is not working. when i give non_overlapping implication/ overlapping implication operator with $stable i am getting error one cycle after the toggles. https://ibb.co/9rkQcN9 https://ibb.co/cyjw1dF ...

    Reply
    UVM
    SVA $stable

  4. Re: I want to write an assertion for checking that the data stable for 16 clock cycles and continue the checking for the next 16 cycles and so on.?How can i write this?

    Posted by adharshh on Apr 30, 2020
    In reply to chr_sue: How about this one, its seems working. a1: assert property (@(posedge tx_bclk) frame_check) property framecheck int local_data; disable iff(!rst ||!tx_frame) (tx_frame, local_data = uart_txd_0) |=> (local_data == uart_txd_o)[=15]); ...

    Reply
    UVM
    SVA $stable

  5. Re: what does the 1 in the notation (1,var_name) in sva means?

    Posted by adharshh on Apr 30, 2020
    In reply to dave_59: Thankyou. ...

    Reply
    UVM

  6. what does the 1 in the notation (1,var_name) in sva means?

    Posted by adharshh on Apr 30, 2020
    UVM Hi, i am new to assertions, i could see in same cases, that its written (1,cnt),(1,cnt==signa_val)..etc.. What exactly does the 1 in the expression do? ...

    Question
    UVM

  7. Re: I want to write an assertion for checking that the data stable for 16 clock cycles and continue the checking for the next 16 cycles and so on.?How can i write this?

    Posted by adharshh on Apr 29, 2020
    In reply to chr_sue: My data is there for 16 cycles, but the checking somehow is starting one cycle after. Is there any other way, instead of using $stable, to check the data stability? ...

    Reply
    UVM
    SVA $stable

  8. Re: Agent without seqeuncer and with driver

    Posted by adharshh on Apr 28, 2020
    In reply to chr_sue: My requirement would be as such, it should be in a configurable way of acting as a transmitter only, receiver only or with both transmitter and receiver parts. that's y i thought of having them as separate agents. ...

    Reply
    UVM
    agents

  9. Re: Agent without seqeuncer and with driver

    Posted by adharshh on Apr 28, 2020
    In reply to chr_sue: so what i consider is that the uart can both transmit and receive at the same time., So in my VIP i am creating two agents. one agent drives frames onto the tx_out line to the DUT and whatever the DUT is transmitting, i will make use ...

    Reply
    UVM
    agents

  10. Re: Agent without seqeuncer and with driver

    Posted by adharshh on Apr 28, 2020
    In reply to chr_sue: So, here's my thing. UART signals-tx_out,rx_in and an interrupt(int_o). DUT Register configurations will be done separately using some other master VIP (like APB,Wishbone..etc). As of me, i am left with uart signals and my uart V ...

    Reply
    UVM
    agents

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