Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Portable Stimulus Basics
      • Introduction to DO-254
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizon - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • MTV - Austin, TX | 12/9
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
      • Debug
      • FPGA Verification
      • All On-Demand Seminars

    • Recording Archive

      • DAC 2019 Session Recordings
      • User2User Silicon Valley 2019
      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • SystemVerilog UVM Advanced
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Advanced OOP
      • UVM Transactions and Sequences
      • UVM Monitors and Agents
      • Functional Verification Library
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - December 2019
      • Verification Horizons - June 2019
      • Verification Horizons - February 2019
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • SystemVerilog
      • Functional Verification Library
Ask a Question
UVM
  • Home /
  • Forums /
  • Search

Forum Search

Results

  1. several parallel sequences

    Posted by UVM_learner6 on Oct 30, 2019
    UVM several parallel sequences fork join_any If I have 3 sequences that are running in parallel and I need to exit the run once 2 out of the 3 sequences are complete, is fork join_any method the best option? Is this fork-join_any solution scalable for a b ...

    Question
    UVM
    several parallel sequences fork join_any

  2. function phase_ready_to_end

    Posted by UVM_learner6 on Oct 21, 2019
    UVM phase_ready_to_end function Hello, I understand that this phase_ready_to_end function can be used in scoreboard perhaps, to extend the time for the last transaction to be completely done instead of floating around. But I have one question- if this is ...

    Question
    UVM
    phase_ready_to_end function

  3. Re: out of order in driver and scoreboard

    Posted by UVM_learner6 on Oct 14, 2019
    In reply to chr_sue: Quote: In reply to UVM_learner6: seq_items comming from the same sequence have always the sam sequence_id, but the transaction_id's are unique.. Storing the transactions which cannot processed immediately in an associative array ...

    Reply
    UVM
    uvm_driver uvm_scoreboard

  4. Re: question on index_id related to comparison

    Posted by UVM_learner6 on Oct 14, 2019
    In reply to dave_59: Thanks- This clarifies my question on index_id usage. Specifically these two points- " I believe it assumes that transactions with different index_id's can be received in any order, but transaction sent with the same index_i ...

    Reply
    UVM
    Cookbook: Scoreboards

  5. question on index_id related to comparison

    Posted by UVM_learner6 on Oct 14, 2019
    UVM Cookbook: Scoreboards https://verificationacademy.com/cookbook/scoreboards#Reporting_and_Recording This OOO comparator uses an index_id function(user written, correct?) to generate an index associated with every transaction and puts it in an associati ...

    Question
    UVM
    Cookbook: Scoreboards

  6. Re: out of order in driver and scoreboard

    Posted by UVM_learner6 on Oct 14, 2019
    In reply to UVM_learner6: Quote: In reply to chr_sue: Quote: In reply to maaroop: Quote: In reply to chr_sue: Hi Ben, There are two ids, one is seq_id and transaction id. These id's are generated by sequencer. In scoreboard, should we compare transac ...

    Reply
    UVM
    uvm_driver uvm_scoreboard

  7. Re: How can we verify a memory whose address location is swapped

    Posted by UVM_learner6 on Oct 14, 2019
    In reply to debashis_paul: I can think of an inefficient method of doing this- but please let me know your thoughts/suggestions. If there is an address decoding problem, lets say there are 10 locations, we can write all 0s to 9 locations and a known patte ...

    Reply
    UVM
    memory verification

  8. block level and top level scoreboard

    Posted by UVM_learner6 on Oct 12, 2019
    UVM one monitor multiple scoreboards Hi, If I have a block level monitor that writes the AP of the agent and the env connects the agent to the block level scoreboard, can I reuse the same monitor/agent at the top level for a top level scoreboard? Essentia ...

    Question
    UVM
    one monitor multiple scoreboards

  9. Re: block level and top level scoreboard

    Posted by UVM_learner6 on Oct 12, 2019
    In reply to chr_sue: Ok, thank you. ...

    Reply
    UVM
    one monitor multiple scoreboards

  10. how does sb identify which agent sent the data?

    Posted by UVM_learner6 on Oct 12, 2019
    UVM Basic clarification needed please. If I have 2 input agents(i_agt) both sending the same transaction type, only one scoreboard, then when we do this connection in the env file, how does the sb distinguish/identify/record which input_agent sent the dat ...

    Question
    UVM

Pages

  • 1
  • 2
  • 3
  • 4
  • next →

Filter by forum:

  • UVM Remove UVM filter

Filter by content type:

  • Reply (23) Apply Reply filter
  • Question (13) Apply Question filter

Filter by solution status

  • Has a solution (5) Apply Has a solution filter
  • Is a solution (2) Apply Is a solution filter

Filter by author:

  • UVM_learner6 Remove UVM_learner6 filter

Filter by question keywords:

  • 0-delay forever loop. (1) Apply 0-delay forever loop. filter
  • burst in-order transactions backpressure (1) Apply burst in-order transactions backpressure filter
  • Cookbook: Scoreboards (1) Apply Cookbook: Scoreboards filter
  • Infinite loop (1) Apply Infinite loop filter
  • maximum runtime (1) Apply maximum runtime filter
  • one monitor multiple scoreboards (1) Apply one monitor multiple scoreboards filter
  • out-of-order scoreboard working example simple (1) Apply out-of-order scoreboard working example simple filter
  • phase_ready_to_end function (1) Apply phase_ready_to_end function filter
  • several parallel sequences fork join_any (1) Apply several parallel sequences fork join_any filter

© Mentor, a Siemens Business, All rights reserved www.mentor.com

Footer Menu

  • Sitemap
  • Terms & Conditions
  • Verification Horizons Blog
  • LinkedIn Group
SiteLock