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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
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      • UVM Forum

    • SystemVerilog Forum

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      • SystemVerilog Forum

    • Coverage Forum

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      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • The Digital Twin: An Aerospace and Defense Revolution - March 9th
      • VIP solutions for Protocol and Memory Verification  - March 11th
      • Advance your Designs with Advances in CDC and RDC - March 23rd
      • Webinar Calendar

    • On Demand Seminars

      • The ABC of Formal Verification
      • I'm Excited About Formal...
      • 2020 Functional Verification Study
      • All On-Demand Seminars

    • Recording Archive

      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • All Recordings

    • Conferences

      • DVCon 2020
      • DAC 2019
      • All Conferences

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Academy Newsletter
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - March 2021
      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • Questa® inFact
      • Functional Verification Library
Ask a Question
UVM #uvm
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  1. Can I declare one time not multiple time for frequently used syntax?

    Posted by UVM_LOVE on Jul 7, 2019
    UVM #uvm Package Hi All, When I use the virtual interface for each class, I declared multiple time like as the below. it seems very inconvenience. Is there any way just one time declare virtual my_interface vintf; and uvm_config_db # (virtual my_interface ...

    Question
    UVM
    #uvm Package

  2. Virtual interface and DUT interface compilation error.

    Posted by UVM_LOVE on Jul 6, 2019
    UVM #uvm uvm virtual interface Dear All, I'm trying to figure out the compilation error when I interface the virtual interface and DUT. https://www.edaplayground.com/x/43dT-testbench.sv `include "uvm_macros.svh" import uvm_pkg::*;   class m ...

    Question
    UVM
    #uvm uvm virtual interface

  3. Connect DUT signals to interface signal problem in virtual interface limitation

    Posted by UVM_LOVE on Jul 5, 2019
    UVM Illegal virtual interface dereference. #uvm Dear all I'm trying to understand virtual interface and uvm_config_db, so I make a simple example https://www.edaplayground.com/x/3zXG As I seen before in Mentor community, Virtual interface has limitat ...

    Question
    UVM
    Illegal virtual interface dereference. #uvm

  4. Can I use while statement substitute by wait statement or vice versa in uvm?

    Posted by UVM_LOVE on Jun 28, 2019
    UVM wait statement while #uvm #systemverilog Hi Can I use while statement substitute by wait statement or vice versa in uvm? // Code your testbench here // or browse Examples module top; bit temp = 1; initial begin $display ("ACODE");   while (t ...

    Question
    UVM
    wait statement while #uvm #systemverilog

  5. How to use...extends uvm_reg_sequence #(uvm_sequence #(uvm_reg_item))?

    Posted by UVM_LOVE on Oct 17, 2018
    UVM #uvm Hi, I came across the code as the below, when I googling. class test_seq extends uvm_reg_sequence # (uvm_sequence # (uvm_reg_item)); uvm_reg rg;... From here, if I want to use or call above class, then how do I call it? especially, How do I use # ...

    Question
    UVM
    #uvm

  6. Should I have to declare the reg_model to the tb and env?

    Posted by UVM_LOVE on Oct 15, 2018
    UVM #uvm Dear All, I'm confused that the declaration of reg_model implementation. and I want to know what is the difference if I don't implement reg_model at env hierarchy. For example, uart_ctrl_tb.sv class uart_ctrl_tb extends uvm_env   uart_c ...

    Question
    UVM
    #uvm

  7. What do they have a relationship between sequencer and adapter which in their hierarchy?

    Posted by UVM_LOVE on Oct 15, 2018
    UVM uvm_sequence uvm_sequencer register adapter #uvm Dear All, I'm come across the point set the APB sequencer and adapter for the register model as the below. uart_ctrl_tb.sv function void ctrl_tb:: connect_phase (uvm_phase phase); reg_model.default ...

    Question
    UVM
    uvm_sequence uvm_sequencer register adapter #uvm

  8. What does "const ref" mean?

    Posted by UVM_LOVE on Oct 14, 2018
    UVM #uvm Dear All, I'm trying to understand the code below, function uvm_sequence_item reg2bus (const ref uvm_reg_bus_op rw);... endfunction 1.What does "const ref" mean? how does it work? 2.What if we use "reg2bus" function which ...

    Question
    UVM
    #uvm

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