Posted by nrllhclb on Jun 25, 2019
UVM #uvm #error #sequence #driver #virtual task run_phase (uvm_phase phase); my_seq_item req; forever begin seq_item_port.get_next_item (req); begin my_vif.write_data <= req. data; end seq_item_port.item_done (); end endtask my code is above, when ru ...
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