Posted by nrllhclb on Jan 30, 2019
UVM #coverage assertion #systemverilog test #uvm Hi, I wrote two assertion in same way, but one of them is covered, but other does not. (a_signal == 16'h48) ##[1:6] $fell(c_signal) |=> it is ok (a_signal == 16'h28) ##[1:6] $fell(c_signal) |=& ...
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