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uvm_hdl_deposit issue

Posted by rag123 on Jan 1, 2021
UVM #uvm Hi, I have a small example where i try to deposit a value to a variable. but it doesnt seem to work? Can any tell me what is wrong here? module xyz; reg [3: 0] cfg; endmodule module bbq; xyz test (); endmodule class basic_test extends uvm_tes ...

Question
UVM

#uvm
clone() method not working

Posted by UVM_SV_101 on Dec 22, 2020
UVM clone() #uvm I tried to use clone method to copy req-rsp but it seems to be failing. I tried to display rsp.data_in but prints '0 all time. req.data_in is getting correct values. Can someone point out what I am missing. Thanks //driver class main ...

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UVM

clone() #uvm
Which region does Testbench use to drive the signal to DUT?

Posted by possible on Dec 14, 2020
UVM timing regions timing control #systemverilog #uvm Suppose, I have a clocking block in the interface(let's say vif) that I am using to connect the testbench to the DUT. I am using the clocking block to drive(vif.cb.var <= XX) and sample the DUT ...

Question
UVM

timing regions timing control #systemverilog #uvm
How you will see assertions failures in VIP Protected? Another than log in UVM

Posted by Subbi Reddy on Dec 9, 2020
UVM #uvm How you will see assertions failures in VIP Protected? Another than log in UVM please mention various ways to see failuers in VIP Protected ...

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UVM

#uvm
Last pushback in queue in scoreboard write method, overriding all values in queue

Posted by possible on Dec 9, 2020
UVM #uvm #UVM #scoreboard UVM monitor #queues #systemverilog I have a monitor and a scoreboard connected through uvm_analysis_port/imp. I am sampling some values in the monitor and using the write function to transport those to the scoreboard. The scorebo ...

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UVM

#uvm #UVM #scoreboard UVM monitor #queues #systemverilog
Ways to reduce simulation time?

Posted by possible on Dec 3, 2020
UVM #uvm #systemverilog simulation How can we reduce simulation time, in general? You can list out things like- 1) Writing better constraints, for example, whatever can be done in post_randomize(), avoid it in do via constraints. ...

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UVM

#uvm #systemverilog simulation
Interview Questions on UVM

Posted by Subbi Reddy on Nov 26, 2020
UVM #uvm #systemverilog I faced conflict to answer for the below Queries in interview,Please give knowledge in the below listed Queries: 1. don’t want to register a sequence to sequencer. What is the alternate macro to uvm_sequence_utils() macro? 2. For d ...

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UVM

#uvm #systemverilog
How driver will request each time to sequencer or sequence need different sequence_item on same interface

Posted by Subbi Reddy on Nov 26, 2020
UVM #uvm #systemverilog How driver will request each time to sequencer or sequence need different sequence_item on same interface ...

Question
UVM

#uvm #systemverilog
Using uvm_config_db in sequence

Posted by UVM_SV_101 on Nov 19, 2020
UVM #uvm #uvm_config_db Hi, I am curious to know how uvm_config_db works to send item from component class to object class. Since component and object class have no visibility to each others hierarchy, how does set-get method work across the classes? I tr ...

Question
UVM

#uvm #uvm_config_db
DUT Speed calculation

Posted by Subbi Reddy on Nov 13, 2020
UVM #uvm How to Know Input and output Speed of the DUT?? ...

Question
UVM

#uvm

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