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Facing Issue with Parameter override from top_tb.

Posted by Pavan Kumar Kollipara on Feb 16, 2022
UVM #UVM #scoreboard #uvm #override #parameter Hello All, I am having query related to the parameter override. DUT: module dut (parameter A = 30, `include parameter_file.sv parameter B = 20) (// DUT ports) // code endmodule parameter file: parameter_file. ...

Question
UVM

#UVM #scoreboard #uvm #override #parameter
Reading enum from a file

Posted by rag123 on Jan 15, 2022
UVM #uvm Hi, I am trying to read a enum from a file, but i dont see that is being driven from Sequence to driver and in the print statements. The example has read.txt which has 2 enum's and reading it from seq_a. Appreciate the help. Enum_from_file ...

Question
UVM

#uvm
UVM ports are never registered with the factory, and covergroups are also never registered with the factory. Why?

Posted by Verif Engg on Dec 1, 2021
UVM #uvm UVM Factory Registration Hi All, This (http://www.sunburst-design.com/papers/CummingsSNUG2012SV_UVM_Factories.pdf) paper brings up a valid point: From the paper: "UVM ports are never registered with the factory, and covergroups are also neve ...

Question
UVM

#uvm UVM Factory Registration
Default sequence in UVM

Posted by Malai_21 on Oct 13, 2021
UVM #uvm #sequence default_sequence Hello all, In UVM, default sequences can be used to start a sequence. I can see many replies in this forum regarding default sequences say "It is not recommended to use default sequences in test". Could you pl ...

Question
UVM

#uvm #sequence default_sequence
uvm scoreboard OOO

Posted by svq on Sep 30, 2021
UVM #uvm #UVM #scoreboard Hi, I came across a interview question to write a scoreboard for for a design which has input id is out of order while output is in order? How do we approach this problem? Should we know the expected first id in this case and jus ...

Question
UVM

#uvm #UVM #scoreboard
Is there any reason for sequence is relative with build_phase and sequencer is relative connect_phase?

Posted by UVM_LOVE on Sep 28, 2021
UVM #uvm I have been trying to understand sequence from test in UVM, I would came across test class as the below, This example looks like "start" used for running sequencer. but as you can see, In build_phase, only implemented with sequence. No ...

Question
UVM

#uvm
base_test doesn't need to implement uvm_config_wrapper?

Posted by UVM_LOVE on Sep 27, 2021
UVM #uvm Dear All, I'm trying to understand the usage of UVM_TESTNAME and some test and sequences. I have made snippet code as the below, When I run " +UVM_TESTNAME=test2 ", then yapp_5_packet sequence has been run, that's what I expec ...

Question
UVM

#uvm
solver fails to solve easy constraints

Posted by nimrodw on Sep 2, 2021
UVM #constraint #randomization #uvm #systemverilog #queues Here are the constraints the solver is unable to solve int int_q [$] = {0, 1, 2}; rand int q_size; rand int rand_int_q [$]; constraint easy_constraint_c {q_size inside {[3: 666]}; rand_int_q. si ...

Question
UVM

#constraint #randomization #uvm #systemverilog #queues
[RAL] Monitoring write and read transactions with a protocol that works in two cycles

Posted by Marc43 on Jul 27, 2021
UVM #UVM #RAL #uvm Hi, I have a protocol that writes in one cycle but takes two cycles to issue a read. The code that notifies the transaction to the adapter is the following: interface dbg_monitor_bfm (input logic clk_i, input logic re_i, input logic w ...

Question
UVM

#UVM #RAL #uvm
Strategy to monitor single signals

Posted by mago1991 on Jul 11, 2021
UVM #uvm #systemverilog UVM monitor Hi, Let`s say we have some interrupt signal that changes without any rules (no protocol). This signal should be compared with the reference signal in the SB. What is the correct way to monitor it? 1. every clock? using ...

Question
UVM

#uvm #systemverilog UVM monitor

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