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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

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      • Functional Safety
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      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Advanced UVM
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      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Upcoming & Featured Events

      • U2U MARLUG - January 26th
      • Creating an Optimal Safety Architecture  - February 9th
      • The ABC of Formal Verification - February 11th
      • Events Calendar
    • On Demand Seminars

      • I'm Excited About Formal...
      • Visualizer Coverage
      • Formal-based ‘X’ Verification
      • 2020 Functional Verification Study
      • All On-Demand Seminars
    • Recording Archive

      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
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    • Mentor Training Center

      • SystemVerilog for Verification
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      • UVM Framework
      • Instructor-led Training
    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • Questa Simulation Coverage Acceleration Apps with inFact
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

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    • Verification Horizons Publication

      • Verification Horizons - November 2020
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Ask a Question
UVM #uvm
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  1. uvm_hdl_deposit issue

    Posted by rag123 on Jan 1, 2021
    UVM #uvm Hi, I have a small example where i try to deposit a value to a variable. but it doesnt seem to work? Can any tell me what is wrong here? module xyz; reg [3: 0] cfg; endmodule   module bbq; xyz test (); endmodule   class basic_test extends uvm_tes ...

    Question
    UVM
    #uvm

  2. clone() method not working

    Posted by UVM_SV_101 on Dec 22, 2020
    UVM clone() #uvm I tried to use clone method to copy req-rsp but it seems to be failing. I tried to display rsp.data_in but prints '0 all time. req.data_in is getting correct values. Can someone point out what I am missing. Thanks //driver class main ...

    Question
    UVM
    clone() #uvm

  3. Which region does Testbench use to drive the signal to DUT?

    Posted by possible on Dec 14, 2020
    UVM timing regions timing control #systemverilog #uvm Suppose, I have a clocking block in the interface(let's say vif) that I am using to connect the testbench to the DUT. I am using the clocking block to drive(vif.cb.var <= XX) and sample the DUT ...

    Question
    UVM
    timing regions timing control #systemverilog #uvm

  4. How you will see assertions failures in VIP Protected? Another than log in UVM

    Posted by Subbi Reddy on Dec 9, 2020
    UVM #uvm How you will see assertions failures in VIP Protected? Another than log in UVM please mention various ways to see failuers in VIP Protected ...

    Question
    UVM
    #uvm

  5. Last pushback in queue in scoreboard write method, overriding all values in queue

    Posted by possible on Dec 9, 2020
    UVM #uvm #UVM #scoreboard UVM monitor #queues #systemverilog I have a monitor and a scoreboard connected through uvm_analysis_port/imp. I am sampling some values in the monitor and using the write function to transport those to the scoreboard. The scorebo ...

    Question
    UVM
    #uvm #UVM #scoreboard UVM monitor #queues #systemverilog

  6. Ways to reduce simulation time?

    Posted by possible on Dec 3, 2020
    UVM #uvm #systemverilog simulation How can we reduce simulation time, in general? You can list out things like- 1) Writing better constraints, for example, whatever can be done in post_randomize(), avoid it in do via constraints. ...

    Question
    UVM
    #uvm #systemverilog simulation

  7. Interview Questions on UVM

    Posted by Subbi Reddy on Nov 26, 2020
    UVM #uvm #systemverilog I faced conflict to answer for the below Queries in interview,Please give knowledge in the below listed Queries: 1. don’t want to register a sequence to sequencer. What is the alternate macro to uvm_sequence_utils() macro? 2. For d ...

    Question
    UVM
    #uvm #systemverilog

  8. How driver will request each time to sequencer or sequence need different sequence_item on same interface

    Posted by Subbi Reddy on Nov 26, 2020
    UVM #uvm #systemverilog How driver will request each time to sequencer or sequence need different sequence_item on same interface ...

    Question
    UVM
    #uvm #systemverilog

  9. Using uvm_config_db in sequence

    Posted by UVM_SV_101 on Nov 19, 2020
    UVM #uvm #uvm_config_db Hi, I am curious to know how uvm_config_db works to send item from component class to object class. Since component and object class have no visibility to each others hierarchy, how does set-get method work across the classes? I tr ...

    Question
    UVM
    #uvm #uvm_config_db

  10. DUT Speed calculation

    Posted by Subbi Reddy on Nov 13, 2020
    UVM #uvm How to Know Input and output Speed of the DUT?? ...

    Question
    UVM
    #uvm

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