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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
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      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
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      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
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      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Creating an Optimal Safety Architecture  - February 9th
      • The ABC of Formal Verification - February 11th
      • Events Calendar

    • On Demand Seminars

      • I'm Excited About Formal...
      • Visualizer Coverage
      • Formal-based ‘X’ Verification
      • 2020 Functional Verification Study
      • All On-Demand Seminars

    • Recording Archive

      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • UVM Framework
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • Questa Simulation Coverage Acceleration Apps with inFact
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

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    • Verification Horizons Publication

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    • Training

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Ask a Question
UVM #uvm #sequence
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  1. Reactive agent for memory storage

    Posted by UVM_SV_101 on Nov 28, 2020
    UVM #uvm #reactive agent #sequence Hi, I have designed an reactive slave as memory storage component. It simple stores data at specified addr with write and read commands. Since I am running the sequence in forever loop. How do I end the simulation? class ...

    Question
    UVM
    #uvm #reactive agent #sequence

  2. Sequencer

    Posted by A_123 on Sep 28, 2020
    UVM #uvm #sequencer #sequence If my seq_item, sequence and sequencer class are same for both master and slave agent,then can i use single seq_item, sequence and sequencer class for both of them? or is it good way to use virtual sequencer in this kind of c ...

    Question
    UVM
    #uvm #sequencer #sequence

  3. Default sequence in UVM

    Posted by Malai_21 on Aug 30, 2020
    UVM #uvm #sequence default_sequence Hello all, In UVM, default sequences can be used to start a sequence. I can see many replies in this forum regarding default sequences say "It is not recommended to use default sequences in test". Could you pl ...

    Question
    UVM
    #uvm #sequence default_sequence

  4. How to write a UVM Sequence

    Posted by rr2007 on Aug 11, 2020
    UVM #uvm #systemverilog #sequence uvm sequence item Hi, I have a doubt in uvm_sequence creation. In the body of a uvm_sequence do I need to write 6 steps for generating a sequence or create req start_item(req) req.randomize() finish_item(req) is these ste ...

    Question
    UVM
    #uvm #systemverilog #sequence uvm sequence item

  5. uvm_sequence

    Posted by voraravi on May 8, 2020
    UVM #sequence #uvm A functionality of sequence states that "You can also use sequences to generate static lists of data items with no connection to a DUT interface." can anyone explain this statement? ...

    Question
    UVM
    #sequence #uvm

  6. Wait_for_item_done() is still in wait state even after item_done() is hit.

    Posted by ganesh shetti on Apr 27, 2020
    UVM #uvm #sequence wait_for_item_done item_done Hi, Following is the code snippet where i am getting the mentioned error. //test run_phase seq_lib.start(env.agent.sequencer); //sequence_lib task body for(i=0;i<4;i++) begin `uvm_create(tr); tr.randomize ...

    Question
    UVM
    #uvm #sequence wait_for_item_done item_done

  7. Sequence in UVM

    Posted by om30 on Apr 22, 2020
    UVM #sequence #uvm #interface wait statement @(posedge clk) begin Hi, I am new to UVM. Can anyone help me in making sequence from this task which was in interface of my sv code. task automatic reg_read_lane (input [`NB_LANES- 1: 0] lane, input [ADDR_WIDTH ...

    Question
    UVM
    #sequence #uvm #interface wait statement @(posedge clk) begin

  8. Error on sequencer- send_request failed to cast sequence item

    Posted by Jose_Iuri on Oct 31, 2019
    UVM #uvm #sequence uvm_fatal casting I build a uvm testbench using RAL to understand the concept of the abstraction layer, but when i run the simulation i have a UVM_FATAL at my sequencer. Quote: UVM_FATAL @ 10: uvm_test_top.m_env.m_agent.m_seqr [m_seqr] ...

    Question
    UVM
    #uvm #sequence uvm_fatal casting

  9. dont drive a value to virtual interface in uvm driver

    Posted by nrllhclb on Jun 25, 2019
    UVM #uvm #error #sequence #driver #virtual task run_phase (uvm_phase phase); my_seq_item req;   forever begin seq_item_port.get_next_item (req); begin my_vif.write_data <= req. data; end seq_item_port.item_done (); end endtask my code is above, when ru ...

    Question
    UVM
    #uvm #error #sequence #driver #virtual

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