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set_report_id_verbosity not working as expected

Posted by rag123 on Jan 19, 2021
UVM #uvm Hi, I am running a UVM TB with set_report_id_verbosity where i set the id and verbosity.I dont see it is getting picked up and the message is not printing. Can any one tell me what is wrong here? Settings inside start_of_simulation_phase env.set_ ...

Question
UVM

#uvm
UVM Verbosity settings for sequence/objects

Posted by rag123 on Jan 19, 2021
UVM #uvm Hi, Is there anyway i can use the UVM_verbosity settings to control messages on uvm sequences or uvm_object? I understand that it is for components. But wondering if there is any other way we can use it instead of turning on and off using +UVM_VE ...

Question
UVM

#uvm
DPI import function not found

Posted by zz8318 on Jan 8, 2021
UVM DPI #uvm I created a cpp file named get_reg_name.cpp as shown below. extern "C" {uint32 get_reg_addr_dpi(const char* reg_name) {uint32 reg_addr;... return reg_addr;}} and in my global file (my_globals.svh) I import it as shown below. import ...

Question
UVM

DPI #uvm
uvm_hdl_deposit issue

Posted by rag123 on Jan 1, 2021
UVM #uvm Hi, I have a small example where i try to deposit a value to a variable. but it doesnt seem to work? Can any tell me what is wrong here? module xyz; reg [3: 0] cfg; endmodule module bbq; xyz test (); endmodule class basic_test extends uvm_tes ...

Question
UVM

#uvm
clone() method not working

Posted by UVM_SV_101 on Dec 22, 2020
UVM clone() #uvm I tried to use clone method to copy req-rsp but it seems to be failing. I tried to display rsp.data_in but prints '0 all time. req.data_in is getting correct values. Can someone point out what I am missing. Thanks //driver class main ...

Question
UVM

clone() #uvm
Which region does Testbench use to drive the signal to DUT?

Posted by possible on Dec 14, 2020
UVM timing regions timing control #systemverilog #uvm Suppose, I have a clocking block in the interface(let's say vif) that I am using to connect the testbench to the DUT. I am using the clocking block to drive(vif.cb.var <= XX) and sample the DUT ...

Question
UVM

timing regions timing control #systemverilog #uvm
how to make sure that the Driver is inactive before calling stop_sequences

Posted by uvm_va_1 on Dec 13, 2020
UVM Stop sequences Inactive Driver #uvm I read it in the warnings before using stop_sequences we have to make sure that the driver is inactive, how can we make sure of that? ...

Question
UVM

Stop sequences Inactive Driver #uvm
How you will see assertions failures in VIP Protected? Another than log in UVM

Posted by Subbi Reddy on Dec 9, 2020
UVM #uvm How you will see assertions failures in VIP Protected? Another than log in UVM please mention various ways to see failuers in VIP Protected ...

Question
UVM

#uvm
Last pushback in queue in scoreboard write method, overriding all values in queue

Posted by possible on Dec 9, 2020
UVM #uvm #UVM #scoreboard UVM monitor #queues #systemverilog I have a monitor and a scoreboard connected through uvm_analysis_port/imp. I am sampling some values in the monitor and using the write function to transport those to the scoreboard. The scorebo ...

Question
UVM

#uvm #UVM #scoreboard UVM monitor #queues #systemverilog
Ways to reduce simulation time?

Posted by possible on Dec 3, 2020
UVM #uvm #systemverilog simulation How can we reduce simulation time, in general? You can list out things like- 1) Writing better constraints, for example, whatever can be done in post_randomize(), avoid it in do via constraints. ...

Question
UVM

#uvm #systemverilog simulation

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