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Two interface driver mechnism.

Posted by sarth21 on Jan 23, 2020
UVM uvm_driver #uvm Hello, Is it possible for a uvm_driver to get values from one interface and drive it to the other. In conventional environments where a sequence is used (req_items) to provide values to interface signals, instead of that an interface s ...

Question
UVM

uvm_driver #uvm
uvm_do_with

Posted by dvuvmsv on Jan 23, 2020
UVM #uvm Hello, To use uvm_do_with, do the sequence_item need to define address,direction as rand? Is it mandatory? Also can you pass reg.address == 32'hFFF0000, directly the value or it need to be a variable? `uvm_do_with(req, {req.address == addr; ...

Question
UVM

#uvm
Using uvm_component to create sequences

Posted by Marc43 on Jan 20, 2020
UVM #uvm sequence uvm_component macros Hi everyone, Can I get a uvm_component to generate sequences? For example, let's say that I have a uvm_component with an analysis_imp listening to a monitor. When the monitor writes into its analysis_port my uvm ...

Question
UVM

#uvm sequence uvm_component macros
Getting an object from parent class to child class

Posted by sj1992 on Jan 16, 2020
UVM #uvm set_config_object get_config_obj environment Hi, I am using UVM1.1 and in this I have a parent env class which sets an object(Ex: set_config_object ("*", "reg_cfg", rif_cfg_h)). I have a child env class which extends this pare ...

Question
UVM

#uvm set_config_object get_config_obj environment
In my extended class, doing a phase jump to jump to pre_reset phase in my main phase. The earlier running sequence is not killed/stopped. Due to that I am facing Fatal saying "sequence alreasdy started". Should I kill/stop this sequnce in doing phase jump

Posted by Subhra Bera on Dec 24, 2019
UVM #phase_jump #uvm In my extended class, doing a phase jump to jump to pre_reset phase in my main phase. The earlier running sequence is not killed/stopped. Due to that I am facing Fatal saying "sequence alreasdy started". Should I kill/stop t ...

Question
UVM

#phase_jump #uvm
UVM limitations.

Posted by sarth21 on Dec 21, 2019
UVM #uvm Emulation what are some of the limitations of UVM. I want to ask this as I got familiar with E-UVM which is called Embedded-UVM which says UVM cannot be used to make multicore testbenches and therefore not used to make H/W tests which are used in ...

Question
UVM

#uvm Emulation
Reading data from the Sequence into Scoreboard

Posted by shivanan on Dec 20, 2019
UVM #uvm config in uvm_sequence class Hi, I had an requirement in which I need to read register value from the sequence upon arrival of the interrupt. The register is not part of the interface, now for comparison I need the read value in my scoreboard. Ho ...

Question
UVM

#uvm config in uvm_sequence class
Unable to pass interface signal by reference to a task

Posted by umeshr1 on Dec 10, 2019
UVM #uvm #interface #systemverilog pass by reference I am trying to pass an interface signal by reference as shown in the below code. But, I see that the simulation hangs at @posedge statement. Even though I have used ref in the compare_freq task, it seem ...

Question
UVM

#uvm #interface #systemverilog pass by reference
Calling DUT Memory initialisation task from uvm_test

Posted by dvuvmsv on Dec 6, 2019
UVM #uvm Hello, I have a task in top.sv which initialises a Memory inside DUT with the contents of the init.mem file. How can I call this task from uvm_test? Thanks JeffD ...

Question
UVM

#uvm
SV Constraint using array of weights

Posted by navjeet1503 on Nov 27, 2019
UVM #systemverilog constraints #uvm #randomization Hi all, Is there a cleaner way to code it to make it more general rather than hard coding it. Problem: var can have values between 0-95 but rate at which we see a random value from 0-31, 32-63, and 64-95 ...

Question
UVM

#systemverilog constraints #uvm #randomization

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