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Command line options to control verbosity settings for different components.

Posted by rag123 on Apr 15, 2021
UVM #uvm I have environment where i have 3 components (test_a,test_b,test_c). I would like to turn off the messages from 2 components and keep 1 of them on. How do i do this through command line? This is the hierarchy-------------------------------------- ...

Question
UVM

#uvm
Casting in UVM

Posted by maazlee on Apr 6, 2021
UVM $cast casting #uvm Hi, I am trying to cast an object in a build phase as shown below. $cast(m_cpu_config[0], name); // where as the "name" is a type string and it holds the design hierarchy "top.a1.b2.c3.dv.rim.get_config_object()" ...

Question
UVM

$cast casting #uvm
Sequence overriding from test.

Posted by sarth21 on Apr 5, 2021
UVM #uvm Application of Factory Overrides Hello, I am trying to override following sequences from build_phase of test. virtual function void build_phase (uvm_phase phase); env_configuration:: type_id:: set_type_override (config_one:: get_type ()); //con ...

Question
UVM

#uvm Application of Factory Overrides
Need of parameterization in UVM

Posted by bachan21 on Apr 5, 2021
UVM #ParameterizedClass #uvm I have observed that the extended UVM classes are often parameterized. For example, user defined driver class. What is the advantage of parameterizing user defined classes? How does it affect the UVM code? ...

Question
UVM

#ParameterizedClass #uvm
Can I get more basic UVM examples to improve my knowledge?

Posted by brain_storm on Apr 3, 2021
UVM #uvm #systemverilog #UVM I have been working as a Design Verification Engineer for a year now and am learning UVM hands-on. But, I would have learned more had I practiced UVM by myself by just having a basic DUT and writing UVM objects+components to v ...

Question
UVM

#uvm #systemverilog #UVM
UVM pipelined driver cookbook

Posted by rag123 on Mar 30, 2021
UVM #uvm I am going through the UVM code on the pipelined driver from cookbook and i dont understand how command phase and data phase execute in parallel? m_bfm.begin_transfer is a blocking call and doesnt not return until the command phase and data phase ...

Question
UVM

#uvm
Why are we driving the read data after two clocks in driver and monitor of a simple memory design?

Posted by brain_storm on Mar 29, 2021
UVM #uvm UVM Driver UVM monitor Design spec: https://verificationguide.com/systemverilog-examples/systemverilog-testbench-example-memory_m/ EDA Code: https://www.edaplayground.com/x/ezS The design spec says, "Read Operation: address and rd_en should ...

Question
UVM

#uvm UVM Driver UVM monitor
how to connect scoreboard with more than one monitor

Posted by Manirama on Mar 29, 2021
UVM #uvm #monitor #UVM #scoreboard hi everybody, In my env class, there is a master agent and slave agent. and i want to connect master agent monitor and slave agent monitor to scoreboard. The query i am having is: 1. do i need to create two scoreboard fo ...

Question
UVM

#uvm #monitor #UVM #scoreboard
Randomization with uvm_do_with

Posted by pankajpattel on Mar 29, 2021
UVM #uvm `uvm_do_with #randomization Hi, I was trying to randomize the the order of read and write through uvm_do_with. In the following code 1.class ahb_wr_rd_seqs extends ahb_base_seq; 2. `uvm_object_utils(ahb_wr_rd_seqs) 3. function new(string name=&qu ...

Question
UVM

#uvm `uvm_do_with #randomization
uvm_backdoor and uvm_frontdoor parallel access to a register

Posted by debdip microsemi on Mar 27, 2021
UVM #uvm #UVM #RAL Hello, I am having one scenario where reg write is happening thru frontdoor access in one uvm_component run_phase. We know It takes couple of clock cycles to complete. For example I am initiating write at 50ns sim time and it is complet ...

Question
UVM

#uvm #UVM #RAL

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