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APB write bin not getting hit

Posted by rag123 on Jun 22, 2022
UVM #uvm I am sampling a coverpoint based on Psel, but it looks like the Read bin and Read after Read gets hit. But for some reason i dont see the write bin getting hit. Here is the sample code. I see in the waves write access are going through. covergrou ...

Question
UVM

#uvm
Reactive agent for memory storage

Posted by UVM_SV_101 on Mar 18, 2022
UVM #uvm #reactive agent #sequence Hi, I have designed an reactive slave as memory storage component. It simple stores data at specified addr with write and read commands. Since I am running the sequence in forever loop. How do I end the simulation? class ...

Question
UVM

#uvm #reactive agent #sequence
Unable to compile a register model using registers of size 2048 bits

Posted by Marc43 on Mar 17, 2022
UVM UVM Questa questasim #uvm uvm register model Hello, I am unable to compile my register model using registers of size 2048 bits. I know that the default size is 64 and we have to do +define+UVM_REG_DATA_WIDTH=2048 when compiling UVM. But it doesn' ...

Question
UVM

UVM Questa questasim #uvm uvm register model
How to display time in femtoseconds for uvm_info statements

Posted by sj1992 on Mar 11, 2022
UVM #uvm UVM_VERBOSITY timescale uvm_info Hi, Is there is command-line option to display time in femtoseconds for uvm_info statements? At present all the uvm statements are printed out in nanoseconds Thanks ...

Question
UVM

#uvm UVM_VERBOSITY timescale uvm_info
Facing Issue with Parameter override from top_tb.

Posted by Pavan Kumar Kollipara on Feb 16, 2022
UVM #UVM #scoreboard #uvm #override #parameter Hello All, I am having query related to the parameter override. DUT: module dut (parameter A = 30, `include parameter_file.sv parameter B = 20) (// DUT ports) // code endmodule parameter file: parameter_file. ...

Question
UVM

#UVM #scoreboard #uvm #override #parameter
how to connect scoreboard with more than one monitor

Posted by Manirama on Feb 6, 2022
UVM #uvm #monitor #UVM #scoreboard hi everybody, In my env class, there is a master agent and slave agent. and i want to connect master agent monitor and slave agent monitor to scoreboard. The query i am having is: 1. do i need to create two scoreboard fo ...

Question
UVM

#uvm #monitor #UVM #scoreboard
Reading enum from a file

Posted by rag123 on Jan 15, 2022
UVM #uvm Hi, I am trying to read a enum from a file, but i dont see that is being driven from Sequence to driver and in the print statements. The example has read.txt which has 2 enum's and reading it from seq_a. Appreciate the help. Enum_from_file ...

Question
UVM

#uvm
Wait_for_item_done() is still in wait state even after item_done() is hit.

Posted by ganesh shetti on Dec 23, 2021
UVM #uvm #sequence wait_for_item_done item_done Hi, Following is the code snippet where i am getting the mentioned error. //test run_phase seq_lib.start(env.agent.sequencer); //sequence_lib task body for(i=0;i<4;i++) begin `uvm_create(tr); tr.randomize ...

Question
UVM

#uvm #sequence wait_for_item_done item_done
UVM ports are never registered with the factory, and covergroups are also never registered with the factory. Why?

Posted by Verif Engg on Dec 1, 2021
UVM #uvm UVM Factory Registration Hi All, This (http://www.sunburst-design.com/papers/CummingsSNUG2012SV_UVM_Factories.pdf) paper brings up a valid point: From the paper: "UVM ports are never registered with the factory, and covergroups are also neve ...

Question
UVM

#uvm UVM Factory Registration
Race condition between write() in UVM scoreboard

Posted by vignesh.kannan on Nov 26, 2021
UVM #monitor #uvm #UVM #scoreboard Assume there is a memory DUT whose interface signals are like: Rd interface: rden, rdaddr Wr interface: wren, wraddr, wdata If the DUT receives both wren and rden in the same clock cycle, it should service write first an ...

Question
UVM

#monitor #uvm #UVM #scoreboard

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