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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

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    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

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      • Register Abstraction Layer
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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
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      • Bus Protocol Coverage
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  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • DAC - Academy Booth #617 | June 3rd - 5th | Las Vegas
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      • UVM 1800.2 & Updated UVM Cookbook
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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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Ask a Question
UVM
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Results

  1. Re: Best way to introduce delay between sequences

    Posted by uvmsd on May 24, 2019
    In reply to chr_sue: Thank you Chris! Right now, I don't really need event trigger in sequence. Yes,you are right about DUT(RAM)behavior. TB should handle it that way when input(with respect to RTL) skew is non-zero. Thank you! ...

    Reply
    UVM
    sequence delays

  2. Best way to introduce delay between sequences

    Posted by uvmsd on May 24, 2019
    UVM sequence delays I have a scenario where in, I just provide a trigger(input control) signal to DUT and series of processes take place inside the DUT. And on TB side, i have to wait for as many clock(around 300,000 clks) before sending another trigger, ...

    Question
    UVM
    sequence delays

  3. Re: How to add user defined functions in uvm_reg and access it from uvm_block with the handle generated by get_registers()

    Posted by dave_59 on May 24, 2019
    In reply to maheshkumar.onsemi: You need to downcast the handle to the proper class variable that can reference the get_storage() method. And the dynamic cast can replace your string name compare vitual task body (); reg_DP_SHIP_LOCK_CONTROL lock_control_ ...

    Reply
    UVM
    uvm register custome fucntion access

  4. How to add user defined functions in uvm_reg and access it from uvm_block with the handle generated by get_registers()

    Posted by maheshkumar.onsemi on May 24, 2019
    UVM uvm register custome fucntion access Hi, I have register definition as below, i have added two user defined functions, 1 is set_default() and other is get_storage(), example code is shown below class reg_DP_SHIP_LOCK_CONTROL extends uvm_reg; rand uvm_ ...

    Question
    UVM
    uvm register custome fucntion access

  5. RAL: functional coverage implementation for registers

    Posted by p@dm@ on May 24, 2019
    UVM Hi, I would like to add coverage for RAL. I have converted my xls file to xml using IP-EACT and giving this xml file to iregGen script, I have generated RAL file. This does not have coverage for registers. Can someone help me on this, How can I add co ...

    Question
    UVM

  6. Re: RAL: functional coverage implementation for registers

    Posted by chr_sue on May 24, 2019
    In reply to p@dm@: Quote: Hi, I would like to add coverage for RAL. I have converted my xls file to xml using IP-EACT and giving this xml file to iregGen script, I have generated RAL file. This does not have coverage for registers. Can someone help me on ...

    Reply
    UVM

  7. Re: RAL: functional coverage implementation for registers

    Posted by cgales on May 24, 2019
    In reply to p@dm@: What features a tool supports is tool specific. This Mentor sponsored forum is not for tool related issues. Please refer to your tool documentation or contact your vendor support team for additional assistance. ...

    Reply
    UVM

  8. Re: RO register with different fields

    Posted by timm on May 24, 2019
    I've got it working. Seems you need to enable auto prediction to get this feature working: default_map.set_auto_predict(1); ...

    Reply
    UVM
    Cookbook: Registers/SequenceExamples

  9. RO register with different fields

    Posted by timm on May 24, 2019
    UVM Cookbook: Registers/SequenceExamples I'm wondering what the appropriate method is for accessing the different fields of an RO register without performing a bus access cycle for every individual field. I was expecting something like this: uvm_stat ...

    Question
    UVM
    Cookbook: Registers/SequenceExamples

  10. Re: Best way to introduce delay between sequences

    Posted by chr_sue on May 23, 2019
    In reply to uvmsd: There is limitation regarding the usage of the uvm_event. The problem with the uvm_event in the sequence is you do not know when the get is issued. Looks like you do in the sequence the get to the config_db before the set was done. With ...

    Reply
    UVM
    sequence delays

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