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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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      • Introduction to ISO 26262
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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

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  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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  1. UART baud rate monitor

    Posted by jayati3108 on Apr 19, 2021
    UVM Has anyone implemented the logic for monitoring the baud rate of UART? How we can do so? If the baud rate deviates or the error is greater then 1% between the desired baud rate and achieved baud rate then it should give error. ...

    Question
    UVM

  2. Re: UART baud rate monitor

    Posted by shanthi on Apr 19, 2021
    In reply to jayati3108: The generation of baud_o depends on the divider latch register(DLR) value & the down counter. Once the value is loaded in DLR, the down counter gets loaded with DLR value & its keep decrementing every clock cycle, when the ...

    Reply
    UVM

  3. How should I do when two package be dependent on each other?

    Posted by designer007 on Apr 19, 2021
    UVM Package if two class be dependent on each other class a class b this could be solved using typedef class a; still the two class package pa; `include "a.sv" endpackage package pb; `include "b.sv" endpackage and pa.sv and pb.sv in di ...

    Question
    UVM
    Package

  4. Re: How should I do when two package be dependent on each other?

    Posted by chr_sue on Apr 19, 2021
    In reply to designer007: If you have the situation you need any type, class or whatever (methods) in different components put this contenet in a seperate package and compile it first. The you can import this content in any other place (component, object) ...

    Reply
    UVM
    Package

  5. Re: UART baud rate monitor

    Posted by jayati3108 on Apr 19, 2021
    In reply to shanthi: ok, can we write like:- lets say required baud rate = 100 allowable baud rate = 99,101 (coz 1% error is allowed) 99>=baud rate<=101 something like this ...

    Reply
    UVM

  6. Re: UART baud rate monitor

    Posted by shanthi on Apr 19, 2021
    You can write an inline assertion assertion in baud generator block to check whether the baud_o is generated properly or not, instead of monitoring it using monitor. ...

    Reply
    UVM

  7. Re: UART baud rate monitor

    Posted by jayati3108 on Apr 19, 2021
    In reply to chr_sue: can you please help me with this assertion? How we can write ...

    Reply
    UVM

  8. Re: How should I do when two package be dependent on each other?

    Posted by designer007 on Apr 19, 2021
    In reply to designer007: //top.sv import base::*; import high::*; `include "testcase0.sv" //if testcase0 not include in base pck, I think this way works module top()... endmodue before this way, I try to add testcase0 in the filelist.f add alway ...

    Reply
    UVM
    Package

  9. Re: How should I do when two package be dependent on each other?

    Posted by designer007 on Apr 19, 2021
    In reply to chr_sue: package base; `include "base_monitor.sv" `include "testcase0.sv" //have a member: h_item hobj; endpackage package high; import base::*; `include "high_monitor.sv" //extends base_monitor `include "h_i ...

    Reply
    UVM
    Package

  10. Re: UART baud rate monitor

    Posted by chr_sue on Apr 19, 2021
    In reply to jayati3108: What you are describing is a typical application for SV Assertions. You should model your behavior in this way. ...

    Reply
    UVM

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