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Regarding Backdoor Access

Posted by MICRO_91 on Sep 26, 2022
UVM Regarding Backdoor Access Hi, I am going through examples on Register Backdoor Access. For the following example:: Backdoor_Access // Within class ral_sys_traffic which is Top Level Register block. function void build (); default_map = create_map (&qu ...

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UVM

Regarding Backdoor Access
Task calling in sequence /Test

Posted by chethan malleshappa1 on Sep 26, 2022
UVM Hi, we have AXI slave tasks in.sv file that will communicate with our DUT. eg: task write (); read(); It is used to work fine in system Verilog test bench approach,now we shifted to UVM methodology,how we can integrate this or how we can use in sequen ...

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UVM
Re: Task calling in sequence /Test

Posted by chethan malleshappa1 on Sep 26, 2022
Any code example will be Good ...

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UVM
Error: formal and actual do not have assignment compatible data types (expecting datatype compatible with 'class uvm_pkg::uvm_component' but found 'packed array' instead).

Posted by kevin488 on Sep 26, 2022
UVM Hi i just tried compiling my testbench top and above mentioned error started popping up `include "uvm_macros.svh" import uvm_pkg::*; //`include "d_ff_item.sv" //`include "sequence.sv" //`include "driver.sv" //`i ...

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UVM
Re: Error: formal and actual do not have assignment compatible data types (expecting datatype compatible with 'class uvm_pkg::uvm_component' but found 'packed array' instead).

Posted by cgales on Sep 26, 2022
In reply to kevin488: Your call to uvm_config_db set() is incorrect. Your first argument ("null" in quotes) is a packed array. The expected argument is of type uvm_component. You want: uvm_config_db # (virtual d_ff_intf):: set (null, "test& ...

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UVM
difference between get_next_item and get?

Posted by lalithjithan on Sep 24, 2022
UVM what is the differnce between get_next_item and get? ...

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UVM
Re: difference between get_next_item and get?

Posted by Shubhabrata on Sep 24, 2022
In reply to S.P.Rajkumar.V: Thanks for the explanation. One more thing I want to clarify is that this response will happen only when we want the connection between the sequencer and driver to be bi-directional. Otherwise, get() is enough to insert into th ...

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UVM
Using uvm_transaction:: end_event for Sequence- Driver Communication

Posted by ABD_91 on Sep 24, 2022
UVM Using uvm_transaction:: end_event for Sequence- Driver Communication I observe the following in Source Code of class uvm_transaction:: virtual task my_sequence:: body ();... start_item (item); item. randomize (); finish_item (item); // return from fin ...

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UVM

Using uvm_transaction :: end_event for Sequence - Driver Communication
why uvm_reg_hw_reset_seq didn't compare the reset value, when volatile bit is "1"?

Posted by Malai_21 on Sep 24, 2022
UVM #RAL #UVM #systemverilog #UVM #UVM #RAL #systemverilog #ralmodelling Hi All, I was trying to use RAL in built sequence(uvm_reg_hw_reset_seq), For few particular register, volatile filed was "1", the sequence actually read register value but ...

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UVM

#RAL #UVM #systemverilog #UVM #UVM #RAL #systemverilog #ralmodelling
Questions to exercise my SystemVerilog, Assertions and UVM skills

Posted by MLearner on Sep 24, 2022
UVM SVA assertion systemverilog systemverilog uvm InterviewQuestions Hey, I'm looking for few sources where i can exercise my UVM, SystemVerilog and Assertions skills by answering few of the programming questions which can be completed within an hour ...

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UVM

SVA assertion systemverilog systemverilog uvm InterviewQuestions

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