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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

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      • Register Abstraction Layer
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    • Coverage Cookbook

      • Introduction
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  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • DVClub Boston - July 31st
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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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Ask a Question
UVM
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Results

  1. uvm agents arbitration

    Posted by Praveen932 on Jul 21, 2019
    UVM UVM Arbitration virtual sequence and sequencer Feeding sequence to multiple agent Hi, I need a clarification on agents arbitration, I have a Design, which contains the arbitration logic,so in my testbench i created 4 agents, and virtual sequencer and ...

    Question
    UVM
    UVM Arbitration virtual sequence and sequencer Feeding sequence to multiple agent

  2. Re: uvm agents arbitration

    Posted by dave_59 on Jul 21, 2019
    In reply to Praveen932: Can you explain better what kind of arbitration you are looking for? "2 or 3 or 4 or 1 agents a send the transactions at a time to DUT" does not make much sense to me. ...

    Reply
    UVM
    UVM Arbitration virtual sequence and sequencer Feeding sequence to multiple agent

  3. what are the key points when implementing Driver?

    Posted by Marina.Miao on Jul 21, 2019
    UVM #driver I am writing a driver for my tb, now I feel puzzled when it comes to the timing, I am ok with other key points like virtual interface and get_next_item() methods, but how to code the main driving part where the timing is concerned? ...

    Question
    UVM
    #driver

  4. Re: what are the key points when implementing Driver?

    Posted by chr_sue on Jul 21, 2019
    In reply to Marina.Miao: Looks like you should have another look tto the basics. What you have to do is to define: (1) a seq_item which contains all your data members you need (2) a sequence which generates seq_items (3) a sequencer/driver pair (4) constr ...

    Reply
    UVM
    #driver

  5. Re: what are the key points when implementing Driver?

    Posted by Marina.Miao on Jul 21, 2019
    In reply to chr_sue: ready is DUT's input signal, so my tb drive this signal, at the same time the driver sample data according to valid and ready, and then encapsulate into items. BTW, I have learned all the basic_uvm course last year or so. ...

    Reply
    UVM
    #driver

  6. Re: what are the key points when implementing Driver?

    Posted by chr_sue on Jul 21, 2019
    In reply to Marina.Miao: I'd recommend you should whatch this course: https://verificationacademy.com/courses/basic-uvm BTW, is ready an input or an output signal? ...

    Reply
    UVM
    #driver

  7. Re: what are the key points when implementing Driver?

    Posted by Marina.Miao on Jul 21, 2019
    In reply to chr_sue: if I want to randomize the 'ready' signal on the bus, how can I implement in my driver? I currently do it in this way: define a rand variable ready in the class driver_cfg, create a substance of driver_cfg in the build_phase ...

    Reply
    UVM
    #driver

  8. set_type_override for parameterized classes

    Posted by saisandeep on Jul 20, 2019
    UVM uvm_set_type_override #uvm UVM COMMANDLINE PROCESSOR class A # (type T = uvm_transaction) extends B `uvm_object_param_utils (A # (T)) //Also tried with `uvm_object_utils().... endclass   class B # (type T = uvm_transaction) extends C `uvm_object_param ...

    Question
    UVM
    uvm_set_type_override #uvm UVM COMMANDLINE PROCESSOR

  9. Re: set_type_override for parameterized classes

    Posted by dave_59 on Jul 20, 2019
    In reply to saisandeep: Paramterized classes cannot be registered with the factory using string names, and the command line only can override classes with string names. Please see http://go.mentor.com/mcem ...

    Reply
    UVM
    uvm_set_type_override #uvm UVM COMMANDLINE PROCESSOR

  10. Re: set_type_override for parameterized classes

    Posted by cgales on Jul 20, 2019
    In reply to saisandeep: You can't override parameterized types from the command line. You may be able to create specialized types with typedefs and use them in an override, but I've never tried. ...

    Reply
    UVM
    uvm_set_type_override #uvm UVM COMMANDLINE PROCESSOR

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