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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Portable Stimulus Basics
      • Introduction to DO-254
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

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    • SystemVerilog Forum

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    • Coverage Forum

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      • Coverage Forum

    • Additional Forums

      • Announcements
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      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizon - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Mentor and TowerJazz Automotive Workshop - Fremont | 11/21
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
      • Debug
      • FPGA Verification
      • All On-Demand Seminars

    • Recording Archive

      • DAC 2019 Session Recordings
      • User2User Silicon Valley 2019
      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • SystemVerilog UVM Advanced
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Advanced OOP
      • UVM Transactions and Sequences
      • UVM Monitors and Agents
      • Functional Verification Library
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - June 2019
      • Verification Horizons - February 2019
      • Verification Horizons - November 2018
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • SystemVerilog
      • Functional Verification Library
Ask a Question
UVM
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  1. UVM vs SystemVerilog

    Posted by Vignesh Raghavan on Nov 19, 2019
    UVM uvm systemverilog Verification Advantages Hi, What are the advantages of using UVM over SystemVerilog for verification? ...

    Question
    UVM
    uvm systemverilog Verification Advantages

  2. Re: UVM vs SystemVerilog

    Posted by to_learn_uvm on Nov 19, 2019
    In reply to Vignesh Raghavan: 1. factory, object creation and overriding 2. config mechanism ...

    Reply
    UVM
    uvm systemverilog Verification Advantages

  3. uvm reg read from uvm-monitor

    Posted by dayalan.natarajan on Nov 19, 2019
    UVM I am trying to read a UVM Register from run_phase of UVM_Monitor and getting the following error Error-[IOUCM] Illegal use of class method dmtcomplex_uvc_pkg, "uvm_pkg::\uvm_reg::read (this.m_dmtcomplex_uvc.m_dmt_reg_block.dmt.dmtint, \this.statu ...

    Question
    UVM

  4. Re: uvm reg read from uvm-monitor

    Posted by zhehuixu_intel on Nov 19, 2019
    In reply to chr_sue: I am positive the parameter was passed to the function correctly. Since it has been used at inside sequence. Just need to some light on how can I use the function inside the uvm_component ...

    Reply
    UVM

  5. Re: uvm reg read from uvm-monitor

    Posted by chr_sue on Nov 19, 2019
    In reply to zhehuixu_intel: reg should be something like this: model.regA. BTW there is no absolute path to the register model becaus ethe reg_model does not belong to the testbench hierarchy. ...

    Reply
    UVM

  6. Re: uvm reg read from uvm-monitor

    Posted by zhehuixu_intel on Nov 19, 2019
    In reply to chr_sue: rm_base_req.read_reg(reg,status,val); reg: the register inside the reg_model. absolute path to the register inside the reg_model status:uvm_reg_status val:32bits wide logic ...

    Reply
    UVM

  7. Re: uvm reg read from uvm-monitor

    Posted by chr_sue on Nov 19, 2019
    In reply to zhehuixu_intel: What are your actual parameters you are using when calling read_reg? ...

    Reply
    UVM

  8. Re: uvm reg read from uvm-monitor

    Posted by zhehuixu_intel on Nov 19, 2019
    In reply to chr_sue: Here is the code I am trying to use: rm_base_req = rm_base_seq::type_id::create("rm_base_req"); rm_base_req.read_reg(reg,status,val); rm_base_seq is extended from uvm_reg_sequence. And this read_reg is the API Provided by th ...

    Reply
    UVM

  9. Re: uvm reg read from uvm-monitor

    Posted by chr_sue on Nov 19, 2019
    In reply to zhehuixu_intel: The question is what is 'read_reg'. The access to a register follows this structure: reg_model_name.reg_map.reg You should show the piece of monitor code which contains the register access and the accurate compile err ...

    Reply
    UVM

  10. Re: uvm reg read from uvm-monitor

    Posted by zhehuixu_intel on Nov 19, 2019
    In reply to chr_sue: The read_reg was implemented inside the driver/BFM. Not inside the monitor. Register model wasn't set up by me. But the base register access sequence has instantiated inside the base register sequence. My question would be what R ...

    Reply
    UVM

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