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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
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    • Featured Courses

      • Portable Stimulus Basics
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      • Power Aware Verification
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      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

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  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

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      • UVM Basics
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      • Register Abstraction Layer
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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
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      • Bus Protocol Coverage
      • Block Level Coverage
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      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Emulation User Forum 2020 | Bengaluru & Hyderabad
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
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    • Recording Archive

      • DAC 2019 Session Recordings
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    • Mentor Training Center

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      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Advanced OOP
      • UVM Transactions and Sequences
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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

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Ask a Question
UVM
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Results

  1. Re: Connecting port and export at different level of hierarchy

    Posted by MICRO_91 on Jan 18, 2020
    In reply to dave_59: class trans extends uvm_transaction; rand int addr; rand int data; rand bit write; endclass   class leaf1 extends uvm_component;   `uvm_component_utils (leaf1)   uvm_blocking_put_port # (trans) out;   function new (string name, uvm_co ...

    Reply
    UVM
    Connecting port and export at different level of hierarchy

  2. Connecting port and export at different level of hierarchy

    Posted by MICRO_91 on Jan 18, 2020
    UVM Connecting port and export at different level of hierarchy I have an agent with producer and consumer components. The producer has leaf1 component with uvm_blocking_put_port. The consumer has leaf2 component with uvm_blocking_put_imp. So typically the ...

    Question
    UVM
    Connecting port and export at different level of hierarchy

  3. Re: Connecting port and export at different level of hierarchy

    Posted by dave_59 on Jan 18, 2020
    In reply to MICRO_91: Can you show some example code, and specifically the warning message you are getting? ...

    Reply
    UVM
    Connecting port and export at different level of hierarchy

  4. Exiting a sequence that has a forever loop

    Posted by tpan on Jan 18, 2020
    UVM I have a reactive sequence that waits for an event for it to send a transaction. Once the transaction is sent it again has to wait for the event to occur. So basically I have this logic inside a forever loop of my sequence. This results in the simulat ...

    Question
    UVM

  5. Re: Exiting a sequence that has a forever loop

    Posted by Rahulkumar on Jan 18, 2020
    In reply to chr_sue: Quote: In reply to Rahulkumar: But, if your sequences have all forever loops no one will stop! Yes, i agree with you at least one sequence should finish. ...

    Reply
    UVM

  6. expecting a right bracket error

    Posted by UVM_LOVE on Jan 18, 2020
    UVM arrary Dear All, I'm trying to make a tiny simple example of systemverilog array as the below, module test (); import uvm_pkg::*; `include "uvm_macros.svh" `include "uart_ctrl_regs.sv"   class test extends uvm_test; uart_ctrl_ ...

    Question
    UVM
    arrary

  7. Re: expecting a right bracket error

    Posted by dave_59 on Jan 18, 2020
    In reply to UVM_LOVE: Syntax errors in Verilog can be very challenging and other tools might be better at explaining the problem based on their experience with the issue. The key point is '$' is not valid to be where you have placed it. The corr ...

    Reply
    UVM
    arrary

  8. Re: Exiting a sequence that has a forever loop

    Posted by chr_sue on Jan 18, 2020
    In reply to Rahulkumar: But, if your sequences have all forever loops no one will stop! ...

    Reply
    UVM

  9. Re: Exiting a sequence that has a forever loop

    Posted by Rahulkumar on Jan 18, 2020
    In reply to chr_sue: Quote: In reply to tpan: Quote: In reply to Rahulkumar: Thanks Rahulkumar. I will try with fork-join_any. I think that might work The fork/join_any will not stop the executung unless you have at least 1 sequence without a forever loop ...

    Reply
    UVM

  10. Control sequences & tasks/functions using virtual sequences

    Posted by Alan1990 on Jan 18, 2020
    UVM #UVM #virtual_sequences Hi All, I have used virtual sequences for controlling multiple sequences. But recently in discussions, I have came across we can control sequences & tasks/functions using virtual sequences. I have browsed a lot, did not fin ...

    Question
    UVM
    #UVM #virtual_sequences

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