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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

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  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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UVM
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Results

  1. Verifying the design using UPF

    Posted by Srinadh on Jun 9, 2023
    UVM UPF Low Power | UPF UPF using UVM Hi, I am trying to integrate UPF file in my test and toggle the power to the design. What I have observed is that some of the variables/signals in the design are going low during power down and are not coming up. When ...

    Question
    UVM
    UPF Low Power | UPF UPF using UVM

  2. Re: Verifying the design using UPF

    Posted by chrisspear on Jun 9, 2023
    In reply to Srinadh: Have a look at this low power introduction. Your request is missing many details. What tools are you using? How was the netlist created? Have you asked your tool vendor for product support? ...

    Reply
    UVM
    UPF Low Power | UPF UPF using UVM

  3. Can we start one sequence onto the driver while it is driving another sequence?

    Posted by Srinadh on Jun 9, 2023
    UVM #sequence #UVM #monitor #sequencer #Agent #TLM_FIFO #UVM #sequence #sequencer #nested_sequence #transaction Can we start one sequence onto the driver while it is driving another sequence? I want the driver to drive a sequence in between another sequen ...

    Question
    UVM
    #sequence #UVM #monitor #sequencer #Agent #TLM_FIFO #UVM #sequence #sequencer #nested_sequence #transaction

  4. Re: Can we start one sequence onto the driver while it is driving another sequence?

    Posted by chrisspear on Jun 9, 2023
    In reply to cgales: UVM divides up the testbench into separate blocks, each with its own job. A sequence creates transaction objects and sends them out. A sequencer receives transaction handles from one or more sequences and arbitrates between them, and s ...

    Reply
    UVM
    #sequence #UVM #monitor #sequencer #Agent #TLM_FIFO #UVM #sequence #sequencer #nested_sequence #transaction

  5. Re: Can we start one sequence onto the driver while it is driving another sequence?

    Posted by cgales on Jun 9, 2023
    In reply to Srinadh: Sequences are started on a sequencer, not a driver. Read the UVM Cookbook section on sequences which explains how to start multiple sequences on the same sequencer. You also want to understand the various arbitration methods as this a ...

    Reply
    UVM
    #sequence #UVM #monitor #sequencer #Agent #TLM_FIFO #UVM #sequence #sequencer #nested_sequence #transaction

  6. Issuse in connecting 2 monitors to scoreboard

    Posted by Sneha M on Jun 9, 2023
    UVM I am trying to connect two monitors to scoreboard by using `uvm_*_imp_decl(), I am getting the below error shown, ALOG: Error: VCP5237 D:/project/xgmi/00_verf_env/00_uvm_env/10_xgmi_tx/axi_scoreboard.sv: (6, 101): Undefined class: uvm_tlm_if_base. The ...

    Question
    UVM

  7. Re: Issuse in connecting 2 monitors to scoreboard

    Posted by cgales on Jun 9, 2023
    In reply to Sneha M: It would be helpful if you post a complete example which shows your issue so that people can provide solutions. Without seeing your code, it is a complete guess as to what the problem is. ...

    Reply
    UVM

  8. What are the guidelines on using uvm_config_db::get() calls inside a uvm_object

    Posted by Venkatesh Maddibande Sheshadrivasan on Jun 9, 2023
    UVM uvm_object and config db::get() Hi I am trying to find the answer for the following question. Is it advisable to use uvm_config_db::get() functions inside constructor of a uvm_object? I need to set the variables of a uvm object from command line and I ...

    Question
    UVM
    uvm_object and config db ::get()

  9. Re: What are the guidelines on using uvm_config_db::get() calls inside a uvm_object

    Posted by Srinadh on Jun 9, 2023
    In reply to Venkatesh Maddibande Sheshadrivasan: HI Venkatsh, Can you enlightem me on how to get something into an object using uvmconfigdb set and get methods? What can be the first and set arguments for the set and get methods? Thanks ...

    Reply
    UVM
    uvm_object and config db ::get()

  10. How to access packet in scoreboard

    Posted by Swathi BN on Jun 9, 2023
    UVM Unable to access packet in scoreboard Hi, How can i create a handler of packet in scoreboard and access it as we do in driver and monitor class. So my agenda is to capture output of DUT from monitor and give it to BFM. I have BFM inside Scoreboard. No ...

    Question
    UVM
    Unable to access packet in scoreboard

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