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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Portable Stimulus Basics
      • Introduction to DO-254
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
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      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
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      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Emulation User Forum 2020 | Bengaluru & Hyderabad
      • DVCon 2020 | San Jose, CA
      • User2User MARLUG - Laurel, MD
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
      • Debug
      • FPGA Verification
      • All On-Demand Seminars

    • Recording Archive

      • DAC 2019 Session Recordings
      • User2User Silicon Valley 2019
      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • All Recordings

    • Mentor Training Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • SystemVerilog Randomization
      • Instructor-led Training

    • Mentor Learning Center

      • Introduction to Visualizer
      • Mastering Questa Learning Path
      • Stimulus Optimization with inFact
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
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    • Verification Horizons Publication

      • Verification Horizons - December 2019
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    • About Us

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      • Contact Us

    • Training

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UVM
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Results

  1. UVM RAL Callbacks for modifying number of bits of data transfer (32b AHB)

    Posted by dolovk on Feb 17, 2020
    UVM #UVM #RAL #uvm #callback #verifcation I am working on UVM register model, where I have registers with various size from 1 to 512 bits. Interface is AHB 32 bits and with HSEL signal I access to 8bits, 16bits and 32 bits. How can I impact using callback ...

    Question
    UVM
    #UVM #RAL #uvm #callback #verifcation

  2. Re: UVM RAL Callbacks for modifying number of bits of data transfer (32b AHB)

    Posted by dolovk on Feb 17, 2020
    In reply to chr_sue: Hi, thank you for your replay. Yes, reg2 is one 24 bit register distributed over 3 addresses. The same reg3. reg2 contains only one bit, and it is presented as 8 bit distributed over one address. (pseudo code) class reg0 extends uvm_r ...

    Reply
    UVM
    #UVM #RAL #uvm #callback #verifcation

  3. Connection between DUT and TB without Interface

    Posted by SriGanesh D on Feb 16, 2020
    UVM #interface DUT Hello all, Is there any method to connect DUT and TB without using Interface in a UVM Environment.? can we use "struct" for this or is there any other method? ...

    Question
    UVM
    #interface DUT

  4. Re: Connection between DUT and TB without Interface

    Posted by dave_59 on Feb 16, 2020
    In reply to SriGanesh D: There are many different ways to connect your DUT to a testbench, but the UVM has settled on an interface based approach as a matter of common practice. And using interfaces does not preclude the use of structs. You may want to re ...

    Reply
    UVM
    #interface DUT

  5. how to create sequence item?

    Posted by user_for_vlsi on Feb 16, 2020
    UVM sequence_item Query Hi, i am coding VIP for one of my DUT, where i have defined interface signals by simply taking out i/o's from DUT. I am little confused to define the sequence_item like whether i need to include all i/o's to the sequence_ ...

    Question
    UVM
    sequence_item Query

  6. Re: Connection between DUT and TB without Interface

    Posted by milin parekh on Feb 16, 2020
    In reply to SriGanesh D: I don't think so that there could be any other way than that, because traditionally it's being a method to connect DUT and tb that is via interface. Further it must be on your application that what you wanted to implemen ...

    Reply
    UVM
    #interface DUT

  7. Re: config_db- parameters for set/get method

    Posted by rgarcia07 on Feb 16, 2020
    In reply to germanbravolopez: I think it is a good idea to revisit a bit your approach to the problem you need to solve, most of the times what may seem a parameter, it is not and can be passed using a config object. Now if you really need to pass the par ...

    Reply
    UVM
    config_db

  8. config_db- parameters for set/get method

    Posted by verif_learner on Feb 16, 2020
    UVM config_db I have a few questions related to config_db working and also parameters related to set/get function. 1) what is the difference between uvm_component context parameter which is the 1st parameter for the set function and string instance name? ...

    Question
    UVM
    config_db

  9. Re: config_db- parameters for set/get method

    Posted by cgales on Feb 16, 2020
    In reply to germanbravolopez: Create a package of design parameters, and use that package to specialize your scoreboard in the environment: typedef my_scoreboard # (param_pkg:: RDW) my_scoreboard_t; ...

    Reply
    UVM
    config_db

  10. How to read and write Through JTAG protocol?

    Posted by VK_18 on Feb 16, 2020
    UVM HOW_TO_READ_AND_WRITE_THROUGH_JTAG Hi all, I am working on soc verification level. For that we are writing and reading from the soc through the JTAG interface in test mode. OR How to read and write from dut through JTAG protocol? please help me for pr ...

    Question
    UVM
    HOW_TO_READ_AND_WRITE_THROUGH_JTAG

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