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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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Ask a Question
Coverage
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Results

  1. Re: If Both functional and code coverage are 100 % then can we say that the verification is complete?

    Posted by Amit G. on Jul 4, 2019
    In reply to kumar-vin: yeah,you can say that. if your functional coverage is also 100% but you can not say it is verified. Sometimes some of the corner cases we are not verified or didn't wrote a test case for that, in that condition some functionali ...

    Reply
    Coverage
    #coverage

  2. Can we exclude AllFalse branch per instance?

    Posted by mushihao on Jun 20, 2019
    Coverage #coverage #exclusion When I use vsim to open ucdb and exclude branches, I found that the allFalse branches are always excluded per module. Is there any option to exclude AllFalse branch per instance? ...

    Question
    Coverage
    #coverage #exclusion

  3. Re: Can we exclude AllFalse branch per instance?

    Posted by dave_59 on Jun 20, 2019
    In reply to mushihao: This forum is not for discussion of tool specific issues. Please read you tools User Manual or contact them directly for support. ...

    Reply
    Coverage
    #coverage #exclusion

  4. functional coverage report

    Posted by Mittal Maru on Jun 13, 2019
    Coverage #coverage #error.ucbd file vcover Questa 10.2c hello, i have used this command to generate the coverage report in system verilog 'vcover report-html-htmldir cov cover.ucdb'. but I am getting the error since my cover.ucdb file is also ge ...

    Question
    Coverage
    #coverage #error .ucbd file vcover Questa 10.2c

  5. Re: functional coverage report

    Posted by thomellis on Jun 13, 2019
    In reply to Mittal Maru: This forum is not for tool related issues. Please refer to your tool documentation or contact your vendor support team for additional assistance. ...

    Reply
    Coverage
    #coverage #error .ucbd file vcover Questa 10.2c

  6. What is the difference between checker and functional coverage?

    Posted by tech_savvy on May 30, 2019
    Coverage If I have written checks on a scenario (like after a certain packet at a defined time next packet should be caome otherwise checker will be fired) so, is it needed to write coverage also?- Is checker a part of VIP or a part of IP? ...

    Question
    Coverage

  7. Re: What is the difference between checker and functional coverage?

    Posted by Marck Boat on May 30, 2019
    Functional Coverage Tracks Your Test Plan. Functional coverage is code that observes the execution of a test plan. As such, it is the code you write to track whether important values, sets of values, or sequences of values that correspond to design or int ...

    Reply
    Coverage

  8. Coverage of all array elements simultaneously

    Posted by TonyFrancis on May 27, 2019
    Coverage Hello, I'm new to Verification and UVM. I have an array "int[31:0] arr" when each element can take an integer between {0...10}. i want to get 100% coverage when all elements united cover all the range. for example i want to get 100 ...

    Question
    Coverage

  9. Re: Coverage of all array elements simultaneously

    Posted by dave_59 on May 27, 2019
    In reply to TonyFrancis: SystemVerilog covergroups cannot deal with arrays, so you'll have to add some code around it covergroup arrcg with sample (int element); coverpoint element {bins allsame = {0: 10}; bins series. = {- 1}; // some value not in t ...

    Reply
    Coverage

  10. Re: If Both functional and code coverage are 100 % then can we say that the verification is complete?

    Posted by kumar-vin on May 27, 2019
    In reply to dave_59: Quote: In reply to kumar-vin: Typical interview question. Code coverage is necessary, but not sufficient. Less than 100% code coverage give you a 100% guarantee of the portion of code that was never tested. 100% functional coverage te ...

    Reply
    Coverage
    #coverage

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