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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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Ask a Question
Coverage
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  1. Coverage save-onexit erroring out

    Posted by kssanath on Sep 13, 2019
    Coverage I am using this do file to save coverage. coverage save-onexit-assert-directive-cvg-codeAll.ucdb run-all I get this error: # ** Error: (vsim-4003) Invalid option '-onexit'. What am I doing wrong here? ...

    Question
    Coverage

  2. Re: Coverage save-onexit erroring out

    Posted by dave_59 on Sep 13, 2019
    In reply to kssanath: This Mentor sponsored public forum is not for discussing too specific issues. Please read your tool's Reference Manual or contact your vendor directly for support. ...

    Reply
    Coverage

  3. Assertion coverage

    Posted by jaswanth_b on Sep 11, 2019
    Coverage Hi, I gave an assertion in test case like this: for (i = 0; i < 10; i ++;) begin if (reg == NULL) begin assert (error == 2) else $error (""); end else begin //some statements end end but in coverage the same assertion line has been s ...

    Question
    Coverage

  4. functioning of cover_group.sample() method?

    Posted by SATYA369 on Sep 7, 2019
    Coverage #coverage I have a few questions regarding cover_group.sample() method. 1.Is it a task or a function? 2.Can anyone give me the implementation code for.sample() method? I know that whenever the line having the.sample method gets executed,it will s ...

    Question
    Coverage
    #coverage

  5. Re: functioning of cover_group.sample() method?

    Posted by SATYA369 on Sep 7, 2019
    In reply to dave_59: Thanks dave Regards SATYA ...

    Reply
    Coverage
    #coverage

  6. Re: functioning of cover_group.sample() method?

    Posted by dave_59 on Sep 6, 2019
    In reply to SATYA369: Section 19.8 Predefined coverage methods of the IEEE 1800-2017 LRM answers your questions. ...

    Reply
    Coverage
    #coverage

  7. specifying "ignore_bins = " in coverpoint bins

    Posted by eh3 on Sep 3, 2019
    Coverage I'm covering values defined as 'typedef enum'. Some of them have dozens of members (enum values), but i only want to cover a few of them in most contexts. I usually want the majority of the values to be in ignore_bins and/or illega ...

    Question
    Coverage

  8. Re: specifying "ignore_bins = " in coverpoint bins

    Posted by kobiyonai on Sep 3, 2019
    In reply to dave_59: Quote: In reply to kobiyonai: Many syntax error result from problems before the line the error message points to. What is PortTypeFec? PortTypeFec is a struct PortTypeFec_s typedef struct packed {PHY_TECH phy_tec; FEC_TYPE fec;} PortT ...

    Reply
    Coverage

  9. Re: specifying "ignore_bins = " in coverpoint bins

    Posted by dave_59 on Sep 3, 2019
    In reply to kobiyonai: Many syntax error result from problems before the line the error message points to. What is PortTypeFec? ...

    Reply
    Coverage

  10. Re: specifying "ignore_bins = " in coverpoint bins

    Posted by kobiyonai on Sep 3, 2019
    In reply to dave_59: hi, i tried this syntax and got " Semicolon (';') symbol is not specified. (in ActNCVerilogPostProcess.pm:237) bins port_type [] = PortTypeFec with (item inside {TestedTypes}); TestedTypes is a SystemVerilog queue- is t ...

    Reply
    Coverage

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