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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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Coverage
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Results

  1. which command we have to use to see which bins hit or which bins is not hit by the questa sim by using the ucdb file

    Posted by sabir shaikh on Jul 30, 2021
    Coverage #coverage #coverage #bins by this command vsim-coverage-vopt axi_top-c-do "coverage save-onexit-directive-cvg-codeall axi_fun_cov.ucdb; run-all;exit" i compile the code but i cant able to check which is the value of the bins hited so an ...

    Question
    Coverage
    #coverage #coverage #bins

  2. Re: which command we have to use to see which bins hit or which bins is not hit by the questa sim by using the ucdb file

    Posted by cgales on Jul 30, 2021
    In reply to sabir shaikh: This Siemens sponsored forum is not for tool related issues. Please refer to your tool documentation or contact your vendor support team for additional assistance. ...

    Reply
    Coverage
    #coverage #coverage #bins

  3. Regex for coverpoint

    Posted by harshavs on Jul 25, 2021
    Coverage regex ctags coverpoints Hello Experts Im new to regular expression, I have a off-topic question. I want a--regex in.ctags to capture coverpoints.--regex-systemverilog=/^\s*\w*\s*\:\s*(\bcoverpoint\b)*\s*(\b\w+\b)/\3/V,coverpoint/ I want to collec ...

    Question
    Coverage
    regex ctags coverpoints

  4. Re: Regex for coverpoint

    Posted by dave_59 on Jul 25, 2021
    In reply to harshavs: use https://regex101.com to help debug your regex errors ...

    Reply
    Coverage
    regex ctags coverpoints

  5. Array of cover points in a covergroup

    Posted by kvenkatv on Jul 14, 2021
    Coverage functional coverage covergroup spctl_hf_intg_cg @(posedge clk); coverpoint `SPCTL_HF_INTG_INST.u_intg.g_regs[0].u_raw_edgedt.sig {bins b[] = {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072, 262144, 5242 ...

    Question
    Coverage
    functional coverage

  6. Re: Array of cover points in a covergroup

    Posted by sundarji on Jul 14, 2021
    In reply to dave_59: Could you able to help me with genvar? With usage and purpose?? ...

    Reply
    Coverage
    functional coverage

  7. How to pass a variable to covergroup with sample function

    Posted by prema9998 on Jul 11, 2021
    Coverage Hi, I am new to SystemVerilog coverage. i am trying out few things. covergroup Timer_cov (int max) with function sample (virtual interface Timer_fcov_if vif); tmr_load_count_cp: coverpoint vif.timer_count {bins tmr_count = {max};} endgroup: Timer ...

    Question
    Coverage

  8. Re: How to pass a variable to covergroup with sample function

    Posted by dave_59 on Jul 11, 2021
    In reply to prema9998: You wrote a covergroup passing an argument (max) to the constructor. The value of the argument is 200, so you will hit on the single bin tar_count when timer_count == 200. For this covergroup, you can either have 0% coverage, or 100 ...

    Reply
    Coverage

  9. Re: How to pass a variable to covergroup with sample function

    Posted by prema9998 on Jul 11, 2021
    In reply to dave_59: Timer_count value is 32 bit random value. It can be any value between 0 to 2^32. I want to sample timer count with respect to max.i want to know how to pass max value from test. ...

    Reply
    Coverage

  10. Re: How to pass a variable to covergroup with sample function

    Posted by dave_59 on Jul 11, 2021
    In reply to prema9998: Not enough code to explain what might be going wrong. What is the value of timer_count when you call sample? ...

    Reply
    Coverage

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