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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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Ask a Question
Coverage
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Results

  1. How do we collect functional coverage on passing test?

    Posted by superUVM on Feb 22, 2020
    Coverage #SystemVerilog #FunctionalCoverage All coverage tools collect coverage on passing test and ignore it on failing test. If I do not use coverage tool, How do I prevent SV simulator from collecting coverage on fail test? ...

    Question
    Coverage
    #SystemVerilog #FunctionalCoverage

  2. Re: How do we collect functional coverage on passing test?

    Posted by cgales on Feb 22, 2020
    In reply to superUVM: It's not clear what your question is. Each test that is run will generate coverage information, regardless if the test passes or fails. It is up to the you to determine what to do with that coverage information. Post-processing ...

    Reply
    Coverage
    #SystemVerilog #FunctionalCoverage

  3. specifying "ignore_bins = " in coverpoint bins

    Posted by eh3 on Jan 30, 2020
    Coverage I'm covering values defined as 'typedef enum'. Some of them have dozens of members (enum values), but i only want to cover a few of them in most contexts. I usually want the majority of the values to be in ignore_bins and/or illega ...

    Question
    Coverage

  4. Re: specifying "ignore_bins = " in coverpoint bins

    Posted by dave_59 on Jan 30, 2020
    In reply to Mohamed_TN: Don't use ignore_bins or default. ...

    Reply
    Coverage

  5. Re: specifying "ignore_bins = " in coverpoint bins

    Posted by Mohamed_TN on Jan 30, 2020
    Hi Dave, in this case the coverage tool will show you all unwanted values (possibles bins), I want to see only what I have specified (A_cp, B_cp, C_cp as in the above example)? ...

    Reply
    Coverage

  6. can 2 different coverpoints in a covergroup have bins with the same same name?

    Posted by sj1992 on Jan 28, 2020
    Coverage #coverage #systemverilog Hi, can 2 different coverpoints in a covergroup have bins with the same same name? covergroup CG2 @ (posedge clk); coverpoint V {bins a = {3, 5}; bins f = {11};}   coverpoint Z {bins a = {2}; bins f = {5};}   endgroup ...

    Question
    Coverage
    #coverage #systemverilog

  7. Re: can 2 different coverpoints in a covergroup have bins with the same same name?

    Posted by sj1992 on Jan 28, 2020
    In reply to dave_59: Thanks Dave. I wanted to check before trying it out. I did not see any errors it worked fine. ...

    Reply
    Coverage
    #coverage #systemverilog

  8. Re: can 2 different coverpoints in a covergroup have bins with the same same name?

    Posted by dave_59 on Jan 28, 2020
    In reply to sj1992: Yes; they are different scopes. Are you getting an error? ...

    Reply
    Coverage
    #coverage #systemverilog

  9. How do I collect coverage for register from multiple address locations

    Posted by superUVM on Jan 23, 2020
    Coverage #SystemVerilog #FunctionalCoverage class reg_functional_coverage extends uvm_subscriber # (axi_seq_item); `uvm_component_utils (reg_functional_coverage)   axi_reg_block regmodel;   covergroup reg_rw_cov; option.per_instance = 1; MODE: coverpoint ...

    Question
    Coverage
    #SystemVerilog #FunctionalCoverage

  10. Re: How do I collect coverage for register from multiple address locations

    Posted by superUVM on Jan 23, 2020
    In reply to dave_59: Any of my_register_* can be written by host. They are arranged in memory as shown above. 1)collect combined coverage of registers in bin MODE when bit [1:0] of any of 128 registers is set. 2)collect combined coverage of registers in b ...

    Reply
    Coverage
    #SystemVerilog #FunctionalCoverage

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