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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IQ
      • Verification IP
      • Static-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Featured & On-Demand

      • Questa Verification IQ - April 11th
      • Continuous Integration
      • SystemVerilog Assertions
      • SoC Design & Functional Safety Flow
      • 2022 Functional Verification Study
      • Design Solutions as a Sleep Aid
      • CDC and RDC Assist
      • Formal and the Next Normal
      • Protocol and Memory Interface Verification
      • Webinar Calendar

    • On-Demand Library

      • Practical Flows for Continuous Integration
      • Lint vs Formal AutoCheck
      • The Three Pillars of Intent-Focused Insight
      • Formal Verification Made Easy
      • Fix FPGA Failures Faster
      • HPC Protocols & Memories
      • FPGA Design Challenges
      • High Defect Coverage
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Complex Safety Architectures
      • Data Independence and Non-Determinism
      • Hierarchical CDC+RDC
      • All On-Demand Recordings

    • Recording Archive

      • Aerospace & Defense Tech Day
      • Exhaustive Scoreboarding
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • Visualizer Debug Environment
      • Preparing for PCIe 6.0: Parts I & II
      • Automotive Functional Safety Forum
      • Siemens EDA Functional Verification
      • Improving Your SystemVerilog & UVM Skills
      • All Webinar Topics

    • Conferences & WRG

      • Industry Data & Surveys
      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
      • All Conferences

    • Siemens EDA Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification IQ
      • Verification Horizons Blog
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - March 2023
      • Verification Horizons - December 2022
      • Verification Horizons - July 2022
      • Issue Archive

    • About Us

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    • Training

      • Learning @OneGlance (PDF)
      • SystemVerilog & UVM Classes
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Ask a Question
UVM
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  1. How to run multiple test scenarios?

    Posted by rahman on Mar 30, 2023
    UVM uvm UVM_TESTNAME test multiple How can i run several tests cases one after another. i.e. I have two test scenarios: my_test1 and my_test2. following command will use only one of the tests. vsim tb_top +UVM_TESTNAME=my_test1 Now how can i run the scena ...

    Question
    UVM
    uvm UVM_TESTNAME test multiple

  2. Why do we use drivers??

    Posted by HanP on Mar 30, 2023
    UVM Hi, i'm a new verfication engineer. I wonder why do we use drivers in UVM. I know the driver's role but i think it's more easy to use driving sequence. if we call the virtual interface in the virtual sequencer and the virtual sequencer ...

    Question
    UVM

  3. Connecting single master to multiple slaves

    Posted by vikasreddy on Mar 30, 2023
    UVM Hi everyone, How to write a code for the scenario: In SPI protocol, we have a 8 bit signal ss_pad_o if it has value 11111111 no slave is selected and if we give all 0's 0th slave is selected, if ss_pad_o gets 11111101 2nd slave is selected. Thank ...

    Question
    UVM

  4. How to get a p_sequencer from a sequence start?

    Posted by UVM_LOVE on Mar 30, 2023
    UVM p_sequencer Hi. I came to know that start_item() is a method of an already running sequence- the sequencer was set when you started it. start_item/finish_item is used to send transactions to a driver, and thus must be connected to a sequencer. and sta ...

    Question
    UVM
    p_sequencer

  5. why do we need multiple test cases?

    Posted by Raghav_Sharma on Mar 30, 2023
    UVM Hi, i am new to uvm, i want to understand why do we need multiple test cases why cant we use a single test, as we can execute our requirement one after the other why make another test? ...

    Question
    UVM

  6. Calling of build phase?

    Posted by Rohan on Mar 29, 2023
    UVM uvm UVM_PHASE build_phase Hi Dave, Who Calls the build phase of each components in UVM hierarchy? ...

    Question
    UVM
    uvm UVM_PHASE build_phase

  7. uvm_hdl_read() works only with STD_LOGIC_VECTOR. (for INTEGER or ENUM (e.g. FSM), only 0 is returned, or a random INTEGER value.

    Posted by vlad_velea on Mar 28, 2023
    UVM uvm_hdl_read STD_LOGIC_VECTOR Hi Using uvm_hdl_read()it only seems to work for STD_LOGIC_VECTOR. If the signal is an INTEGER or ENUM (e.g. FSM), only 0 is retured, or an implausible value with an integer signal... Is this something wrong or does it ju ...

    Question
    UVM
    uvm_hdl_read STD_LOGIC_VECTOR

  8. How can I configure two agents with Active and Passive?

    Posted by Yeptho on Mar 26, 2023
    UVM Hi, I have two agents in one environment. Considering agt1(active) and agt2(passive), I have two agent config files and using uvm_config_db both the config is set in the testbase class and I'm retrieving back using get method in agt1 and agt2. Ca ...

    Question
    UVM

  9. Hi,can i know the mistake which causes below error?

    Posted by Adharsh_07 on Mar 25, 2023
    UVM class A_agent extends uvm_agent; `uvm_component_utils(A_agent) function new(string name = "",uvm_component parent); super.new(name,parent); endfunction driver h_driver; inp_mon h_inpm; sequencer h_seqr; function void build_phase(uvm_phase ph ...

    Question
    UVM

  10. Is it legal to have a handle to a class inside the same class?

    Posted by ANASKU on Mar 25, 2023
    UVM Is this below code the right way of coding? This seems to work, but I am not sure if will be any issues with the code? like performance e.t.c. Thanks in advance. typedef ext_class_1; typedef ext_class_2; typedef ext_class_3;   class base_class; base_c ...

    Question
    UVM

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