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Long delay not working properly in Verilog

Posted by Dev_Engine on Apr 27, 2023
SystemVerilog Verilog Altera quartus cyclone II Hello, I want to implement a delay of several hours for a bit to go high and drive the rest of the circuit. Using Quartus II 13.0sp1 and running the code on a simple Altera Cyclone II. I know vendor question ...

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SystemVerilog

Verilog Altera quartus cyclone II
Running UVM example on MODELSIM- ALTERA 10.1d

Posted by Abhyudha on Mar 17, 2015
UVM System-verilog Verilog uvm modelsim Altera I want to compile and simulate this simple UVM example using Modelsim-Altera 10.1d tool. module uvm_first_ex; import uvm_pkg::*; `include "uvm_macros.svh" initial begin `uvm_info ("ID", &q ...

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UVM

System-verilog Verilog uvm modelsim Altera