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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

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    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

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  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
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      • Analysis Components & Techniques
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      • Register Abstraction Layer
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    • Coding Guidelines & Deployment

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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
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      • Bus Protocol Coverage
      • Block Level Coverage
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      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • The Digital Twin: An Aerospace and Defense Revolution - March 9th
      • VIP solutions for Protocol and Memory Verification  - March 11th
      • Advance your Designs with Advances in CDC and RDC - March 23rd
      • Webinar Calendar

    • On Demand Seminars

      • The ABC of Formal Verification
      • I'm Excited About Formal...
      • 2020 Functional Verification Study
      • All On-Demand Seminars

    • Recording Archive

      • Improving Your SystemVerilog & UVM Skills
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    • Conferences

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    • Mentor Learning Center

      • SystemVerilog Fundamentals
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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

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    • Verification Horizons Publication

      • Verification Horizons - March 2021
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    • About Us

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Results

  1. Constraint to generate an array of random numbers where a certain value is repeated fixed number of times

    Posted by nachiketag on Mar 6, 2021
    SystemVerilog Lets assume I have the below class: class numberGen; int i; rand bit[7:0] arr[100]; function new(); i = 5; endfunction endclass I want to write a constraint so that 10 elements of the array arr have the value of 5, if i call randomize() on a ...

    Question
    SystemVerilog

  2. Re: Constraint to generate an array of random numbers where a certain value is repeated fixed number of times

    Posted by sasi_8985 on Mar 6, 2021
    In reply to sasi_8985: Hi all, I had tried below code and i am getting an error like this:- xmsim: * W, SVRNDF (. / testbench.sv, 39 | 17): The randomize method call failed. The unique id of the failed randomize call is 0. Observed simulation time: 0 FS + ...

    Reply
    SystemVerilog

  3. how to get configuration from sequence

    Posted by Danil on Mar 6, 2021
    UVM uvm_config_db #(...)::get() Hello, I need to set my configuration using uvm_config_db# in test and get it from my sequnce. I'm doing this, but it doesn't work. How should I properly use set/get methods in this case? class pcc_config extends ...

    Question
    UVM
    uvm_config_db #(...)::get()

  4. Re: how to get configuration from sequence

    Posted by meenakshi bommu on Mar 6, 2021
    In reply to bmorris: Quote: In reply to Danil: Danil, I am currently doing the exact scenario you described; no problems. Can you confirm a couple things: 1. Make sure your set () is not in the run_phase; place it in the build, connect, or end of elaborat ...

    Reply
    UVM
    uvm_config_db #(...)::get()

  5. Re: how to constraint a variable in extended class based on a variable in base class?

    Posted by dave_59 on Mar 6, 2021
    In reply to yr: Once again, please use code tags making your code easier to read. I have added them for you. You have created two distinct objects and only randomized one of them. When you call vlanobj.display(), vlan still has its initial value. Have you ...

    Reply
    SystemVerilog
    #systemverilog #constraint Extended Class

  6. how to constraint a variable in extended class based on a variable in base class?

    Posted by yr on Mar 6, 2021
    SystemVerilog #systemverilog #constraint Extended Class Below is an example I was trying. Even though the kind variable is being randomized to both II and IEEE, I see that in the extended class constraint, it only prints kind as II and thus keeps vlan var ...

    Question
    SystemVerilog
    #systemverilog #constraint Extended Class

  7. phases

    Posted by anvesh dangeti on Mar 6, 2021
    UVM UVM phase scheduler UVM phases Which uvm phase is top- down, bottom – up & parallel? I got different answers about uvm phases approach.- build_phase() & final_phase() are Top-Down, rest all phases are Bottom-Up.- build phase which is top-down ...

    Question
    UVM
    UVM phase scheduler UVM phases

  8. Re: phases

    Posted by anvesh dangeti on Mar 6, 2021
    according to above source the build() phase in UVM executed in a Top- Down fashion and the other phases in Bottom- Up fashion but I check below link they mentioned differently in verification guide Your text to link here... and run phase will executed in ...

    Reply
    UVM
    UVM phase scheduler UVM phases

  9. Bus Functional model

    Posted by Krishna9 on Mar 6, 2021
    UVM BFM When someone says BFM what UVM components are they referring to? ...

    Question
    UVM
    BFM

  10. Re: Bus Functional model

    Posted by dave_59 on Mar 6, 2021
    In reply to Krishna9: https://verificationacademy.com/forums/uvm/what-difference-between-driver-and-bfm#reply-53187 ...

    Reply
    UVM
    BFM

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