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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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Results

  1. Sequence for Register Write and Read Check

    Posted by rupeshblr on Nov 29, 2020
    UVM Hi, I am not using the RAL model for Register Rd-Wr and POR check. I have created my own processor based Wr and read task (hooked Processor Vip). and i want to create one sequence to verify all the registers of one blocks. Dummy Code: virtual task bod ...

    Question
    UVM

  2. Re: Sequence for Register Write and Read Check

    Posted by chr_sue on Nov 29, 2020
    In reply to rupeshblr: I do not know how many registers you have. If it is as mall number it is not useful to employ the RAL. The code you are showing is very simple. ou do not work with randomized data. But this is necessary. I recommedn the following so ...

    Reply
    UVM

  3. Valid args to randomize() Method

    Posted by Have_A_Doubt on Nov 29, 2020
    SystemVerilog Valid args to randomize() Method Hi all, I am trying to figure out what is a valid arg. to randomize() method. // Code I class Main;   rand bit [1: 0] b [2];   endclass   Main m;   initial begin   m = new ();   if (m. randomize (b [1])) // l ...

    Question
    SystemVerilog
    Valid args to randomize() Method

  4. Re: Valid args to randomize() Method

    Posted by dave_59 on Nov 29, 2020
    In reply to Have_A_Doubt: Code I is illegal, the arguments to the randomize method must be variable names. Adding an index makes it a select expression. Code II is not as clear, but I see no reason to code like this. You wind up with two active random var ...

    Reply
    SystemVerilog
    Valid args to randomize() Method

  5. difference between functions

    Posted by venkatesh konduru on Nov 29, 2020
    SystemVerilog static functions what is diffrence between function static void display_packets_created(); and static function void display_packets_created(); methods? ...

    Question
    SystemVerilog
    static functions

  6. Re: difference between functions

    Posted by dave_59 on Nov 29, 2020
    In reply to venkatesh konduru: You should never need to write function static, and it is illegal if defining a class method. See https://verificationacademy.com/forums/systemverilog/“static-task”-vs.-“task-static”#reply-53391 ...

    Reply
    SystemVerilog
    static functions

  7. Re: difference between functions

    Posted by Meet Patel on Nov 29, 2020
    static function is a function whose scope is static. I mean, a static function remains same for ALL the objects of a class. In system memory, the function is stored at a single place and all the objects access that function memory. ‘function static‘ is an ...

    Reply
    SystemVerilog
    static functions

  8. Re: Sequence for Register Write and Read Check

    Posted by rupeshblr on Nov 29, 2020
    In reply to cgales: dont have any specific reason. I know, Using RAL its easier. But still it will be vey helpful if you suggest anything other than RAL ...

    Reply
    UVM

  9. Re: Sequence for Register Write and Read Check

    Posted by cgales on Nov 29, 2020
    In reply to rupeshblr: Why do you not want to use the RAL model? It makes things significantly easier and contains automated sequences for testing. ...

    Reply
    UVM

  10. reset methodology in UVM environment

    Posted by shimonc on Nov 29, 2020
    UVM Hi UVM forum, I need to implement in my UVM environment a reset methodology. It means that reset (actually few of them but lets start with one) can assert at any time in the simulation. not necessarily in reset_phase but mainly in run_phase. Is there ...

    Question
    UVM

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