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Re: constraint for 5 bits set and consecutively set for 80% of the time

Posted by dave_59 on Nov 30, 2022
In reply to peter: A state variable is a non random variable. It gets treated like a constant value as far as the constraint is concerned. ...

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SystemVerilog

#constraint #randomization
constraint for 5 bits set and consecutively set for 80% of the time

Posted by verif_eng_20 on Nov 30, 2022
SystemVerilog #constraint #randomization Hi, I have tried to code for the scenario and found below is not working (always first 5 bits are set to 1) when set_consctv is 1. Please let me know the issue. class a; rand bit [99: 0] var1; rand bit set_consctv; ...

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SystemVerilog

#constraint #randomization
Re: How does uvm_component go to Clean-up phases from Run_phases?

Posted by cgales on Nov 30, 2022
In reply to dv_lee86: The build phases and cleanup phases are implemented as functions, so they are all expected to complete in 0 time. The run phases will consume time, so the UVM scheduler will fork these tasks in parallel. After forking the tasks, the ...

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UVM

uvm_component #run_phase phase_raise_objection
How does uvm_component go to Clean-up phases from Run_phases?

Posted by dv_lee86 on Nov 30, 2022
UVM uvm_component #run_phase phase_raise_objection Hi, From what I've understood so far, uvm_components have each phase so that all objects are able to go to the next phase when all the same phase of every uvm_component objects are finished. If so, a ...

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UVM

uvm_component #run_phase phase_raise_objection
Re: All Values of a coverpoint need to be hit at same time

Posted by MICRO_91 on Nov 30, 2022
In reply to Thirumal: I believe you have the following requirement:: typedef enum bit [1: 0] {ADD, SUB, MUL, DIV} opcode_type; // Missing keyword ' bit ' above opcode_type opcode; covergroup gc; // sample() Must be called same: coverpoint ...

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SystemVerilog

#coverage #bins #system verilog #coverage #with clause #coverpoints coverpoint sample #coverage #option.goal #option.weight #goal #weight array covergroup functional coverage
All Values of a coverpoint need to be hit at same time

Posted by Thirumal on Nov 30, 2022
SystemVerilog #coverage #bins #system verilog #coverage #with clause #coverpoints coverpoint sample #coverage #option.goal #option.weight #goal #weight array covergroup functional coverage Hi, I have a scenario where I have 3 opcodes and a 4 bit ID. How d ...

Question
SystemVerilog

#coverage #bins #system verilog #coverage #with clause #coverpoints coverpoint sample #coverage #option.goal #option.weight #goal #weight array covergroup functional coverage
Extracting a number from a string in system verilog

Posted by rubendah on Nov 30, 2022
SystemVerilog #systemverilog #systemverilog #Strings Hi all, Let's say I have the following string: string my_str = "Packet #3 size is 1500B"; I would like to extract the packet size (here 1500) and to assign it to an int. What will be the ...

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SystemVerilog

#systemverilog #systemverilog #Strings
Re: Extracting a number from a string in system verilog

Posted by DLIS on Nov 30, 2022
In reply to dave_59: Hi Dave, A follow up question on this if I may- I have a match using uvm_re_match (returning 0- to my understanding it means the string matches) How do I extract the actual searched sub-strings after the match? I can't find any m ...

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SystemVerilog

#systemverilog #systemverilog #Strings
Re: All Values of a coverpoint need to be hit at same time

Posted by Thirumal on Nov 29, 2022
Thanks Shubhabrata for the reply. I think you got it in a different way. Let me make it clear. bit [3:0] id; typedef enum[1:0] {ADD, SUB,MUL} opcode_type; opcode_type opcode; covergroup g; // Same and Diff opcodes means back to back same and diff opcodes. ...

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SystemVerilog

#coverage #bins #system verilog #coverage #with clause #coverpoints coverpoint sample #coverage #option.goal #option.weight #goal #weight array covergroup functional coverage
Re: All Values of a coverpoint need to be hit at same time

Posted by Shubhabrata on Nov 29, 2022
In reply to Thirumal: Could you write a few lines of code, please? It isn't easy to get what you wrote. As far as I observed, your question looks like this- bit [3: 0] id; covergroup g; a: coverpoint id {.......} //opcode_1 b: coverpoint id {.......} ...

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SystemVerilog

#coverage #bins #system verilog #coverage #with clause #coverpoints coverpoint sample #coverage #option.goal #option.weight #goal #weight array covergroup functional coverage

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