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Register

Posted by Design Engineer on Jul 10, 2020
SystemVerilog #systemverilog Consider reg A,B How to declare the address for this register as 100,110? ...

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SystemVerilog

#systemverilog
Re: Register

Posted by ben@SystemVerilog.us on Jul 10, 2020
In reply to Design Engineer: I thought this question was previously answered. Is this what you meant? // Consider 2 register namely A,B // I need to define the address for the register as 0x102,0x104 module m (input logic clk, rd, wr, input logic [15: 0] ...

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SystemVerilog

#systemverilog
Self checking Testbench

Posted by Lavin786 on Jul 10, 2020
SystemVerilog #systemverilog #enum #classes #constraints #verilog #testbench self-checking test-bench for a (16x8)Dual-port Synchronous RAM Implement reference model in the Test-bench, anyone knows how to do this. ...

Question
SystemVerilog

#systemverilog #enum #classes #constraints #verilog #testbench
Re: Self checking Testbench

Posted by ben@SystemVerilog.us on Jul 10, 2020
In reply to Lavin786: Quote: self-checking test-bench for a (16x8)Dual-port Synchronous RAM Implement reference model in the Test-bench, anyone knows how to do this. Are you asking about the methodologies to test a (16x8)Dual-port Synchronous RAM? There a ...

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SystemVerilog

#systemverilog #enum #classes #constraints #verilog #testbench
How control the parameter value from test.

Posted by bijal thakkar on Jul 10, 2020
UVM Parameters are constant. So how to change the parameter value in test? If parameter is defined in class? ...

Question
UVM
Re: How control the parameter value from test.

Posted by dave_59 on Jul 10, 2020
In reply to bijal thakkar: Parameters are run-time constants. The test is a run-time procedure. It's too late to change a parameter by the time you get to the test. You can try using a variable in a configuration object instead of a parameter to cont ...

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UVM
Forcing random value into signals

Posted by ashlanK on Jul 10, 2020
SystemVerilog force signal #randomization #systemverilog Hi, I am trying force the signals to random value which will change at each loop. I read somewhere that class data cannot be passed into force/assign the signals. So, I tried to create static signal ...

Question
SystemVerilog

force signal #randomization #systemverilog
uvm_set_action options can demote UVM_ERROR,UVM_FATAL

Posted by gowsan on Jul 9, 2020
UVM Hi Team, Use of the uvm_set_action in this way can demote the UVM_ERROR? command line option:- simv +UVM_TESTNAME=test1 +uvm_set_action=uvm_test_top.*_uvc.*_env.*_slave_env.env.driver*,_ALL_,_ALL_,UVM_NO_ACTION'->From the driver block will i n ...

Question
UVM
Re: uvm_set_action options can demote UVM_ERROR,UVM_FATAL

Posted by gowsan on Jul 9, 2020
In reply to dave_59: Hi Team, "The uvm_set_action command above turns off/filters all messages from the driver" Above statement,within("") includes that all messages means even UVM_ERROR,UVM_FATAL also will be turned off? Best Regards, ...

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UVM
Backdoor RAL read issue

Posted by alexkidd84 on Jul 9, 2020
UVM backdoor backdoor read_wrie #uvm bit size Hi, I'm trying to read (RAL) via BACKDOOR this RW register (40 bits width), after performing a FRONTDOOR write (the FRONTDOOR read works properly): uvm_reg urm_reg [$]; uvm_reg_field urm_reg_field [$]; ...

Question
UVM

backdoor backdoor read_wrie #uvm bit size

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