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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

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      • Functional Safety
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    • Methodologies

      • UVM - Universal Verification Methodology
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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Portable Stimulus Basics
      • Introduction to DO-254
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
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      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
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      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Emulation User Forum 2020 | Bengaluru & Hyderabad
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
      • Debug
      • FPGA Verification
      • All On-Demand Seminars

    • Recording Archive

      • DAC 2019 Session Recordings
      • User2User Silicon Valley 2019
      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • SystemVerilog UVM Advanced
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Advanced OOP
      • UVM Transactions and Sequences
      • UVM Monitors and Agents
      • Functional Verification Library
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

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    • Verification Horizons Publication

      • Verification Horizons - December 2019
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      • Verification Horizons - February 2019
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • SystemVerilog
      • Functional Verification Library
Ask a Question
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Results

  1. Variiables

    Posted by SidRaj on Jan 18, 2020
    SystemVerilog Variable use Is internal variable declared in dut, can be used by scoreboard? ...

    Question
    SystemVerilog
    Variable use

  2. Re: Variiables

    Posted by ben@SystemVerilog.us on Jan 18, 2020
    In reply to SidRaj: I can can give you guidelines. I presume that you have a requirement document. Ben ...

    Reply
    SystemVerilog
    Variable use

  3. Connecting port and export at different level of hierarchy

    Posted by MICRO_91 on Jan 18, 2020
    UVM Connecting port and export at different level of hierarchy I have an agent with producer and consumer components. The producer has leaf1 component with uvm_blocking_put_port. The consumer has leaf2 component with uvm_blocking_put_imp. So typically the ...

    Question
    UVM
    Connecting port and export at different level of hierarchy

  4. Re: Connecting port and export at different level of hierarchy

    Posted by MICRO_91 on Jan 18, 2020
    In reply to dave_59: class trans extends uvm_transaction; rand int addr; rand int data; rand bit write; endclass   class leaf1 extends uvm_component;   `uvm_component_utils (leaf1)   uvm_blocking_put_port # (trans) out;   function new (string name, uvm_co ...

    Reply
    UVM
    Connecting port and export at different level of hierarchy

  5. Re: Variiables

    Posted by SidRaj on Jan 18, 2020
    In reply to ben@SystemVerilog.us: Thanks for clearing my doubts.Can I send my code to your mail id so that you can help to find where I am getting wrong.? ...

    Reply
    SystemVerilog
    Variable use

  6. Matrix multiplication

    Posted by PJ on Jan 18, 2020
    SystemVerilog Hi all, I try to coded for matrix multiplication with N*N. am getting some errors related to that could you please help me. http://www.edaplayground.com/x/3ESR Thanks, ...

    Question
    SystemVerilog

  7. Re: Matrix multiplication

    Posted by sai yamuna chakka on Jan 18, 2020
    In reply to PJ: Did u get the output for matrix multiplication for N*N matrix? ...

    Reply
    SystemVerilog

  8. Re: Automatic variable

    Posted by yourcheers on Jan 18, 2020
    Thanks Rahul & Dave. Helpful information. ...

    Reply
    SystemVerilog

  9. Automatic variable

    Posted by yourcheers on Jan 18, 2020
    SystemVerilog module test; initial begin for (int i = 0; i < 5; i ++) begin fork begin automatic int l = i; $display (i, l); end join_none end end endmodule What are the rules for automatic variable declaration? Why in the above code "l" is n ...

    Question
    SystemVerilog

  10. Is there a way to check if variables within a OVM component is registered to the factory via OVM field automation macros?

    Posted by wchua on Jan 18, 2020
    OVM OVM field automation macros Say I have a transaction item class like below: class tx_item extends ovm_sequence_item; logic a; logic b;   `ovm_object_utils_begin (tx_item) `ovm_field_int (a, OVM_ALL_ON) `ovm_field_int (b, OVM_ALL_ON) `ovm_object_utils_ ...

    Question
    OVM
    OVM field automation macros

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