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Backdoor access to memory issue

Posted by Lukas102 on Nov 12, 2020
UVM #uvm Hello, I have an issue related with backdoor access to memory i.e. path appears to be fine, also +acc visibility is turned on, however the access throws an error: # UVM_ERROR: Unable to read value from 'dut_top.dut_wrapper.dut.module_path.me ...

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UVM

#uvm
the PCIe test do not completed sometimes, phase stucks

Posted by Levard on Nov 6, 2020
UVM #uvm Hello everyone! Now I work with my former colleague's PCIe with PHY VIP environment. I rewrote a sequence with asserting and deasserting interrupts. Some tests (with some seeds) are completed successfully PCIE INFO-- (uvm_phase.svh: 1345) [P ...

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UVM

#uvm
write a task to wait a signal to go high(initially signal is low) within 50ns

Posted by Subbi Reddy on Nov 4, 2020
SystemVerilog #systemverilog #uvm one bit signal coming from design, its a pulse kind of signal, Initially signal is low. write a task to wait a signal to go high within 50ns timeout then end the task, if signal is taking morethan timeout to go high then ...

Question
SystemVerilog

#systemverilog #uvm
how to change RTL signals during the simulation in the testbench

Posted by zz8318 on Nov 3, 2020
UVM #uvm #verilog #testbench I'd like to ask a question how to change RTL signals during the simulation in our TB? Usually we will force some of signals (most of them are input for our DUT) in the top like below. module top;... initial begin force tb ...

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UVM

#uvm #verilog #testbench
Regarding forcing a value through sequence

Posted by kritikagoell on Nov 1, 2020
UVM #uvm force signal uvm_hdl_force Hi All, I am using uvm_hdl_force in my test environment. I was trying the same to assert/control the signal value from sequence, but didn't succeed. Giving rtl path hierarchy in test environment or in test itself i ...

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UVM

#uvm force signal uvm_hdl_force
What is the difference between uvm_config_db::set() and set_config*() functions in uvm?

Posted by Arun_Rajha on Oct 30, 2020
UVM #uvm Does both the functions does the same operation? ...

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UVM

#uvm
Multiple `ifndef requirement

Posted by xfinity on Oct 29, 2020
UVM #uvm #systemverilog Hello, I have requirement where a certain piece of code must not be executed: `ifndef BRIDGE and TOP $display ("Don't execute this "); `endif This gives compile error: I can do this `define BRIDGEandTOP and then ...

Question
UVM

#uvm #systemverilog
verifying values a and b values using assertions

Posted by Subbi Reddy on Oct 16, 2020
SystemVerilog #systemverilog #uvm Suppose when bit a is high then next cycle, bit [1:0]b is 11 in first cycle and second cycle is b=00 and third cycle b=11... Continuous, suppose in between a=0 then again whenever 'a' becomes 1 then b value is 1 ...

Question
SystemVerilog

#systemverilog #uvm
How to find pending AXI Outstanding transactions in queue

Posted by Subbi Reddy on Oct 15, 2020
SystemVerilog #systemverilog #uvm 1. How to count the outstanding transactions in AXI? 2. will get responses from slave for outstanding transactions? ...

Question
SystemVerilog

#systemverilog #uvm
How to certify RTL working at last moment

Posted by Subbi Reddy on Oct 15, 2020
SystemVerilog #systemverilog #uvm 90% verification done, after in RTL some changes went and without effect the previous results, how I can conclude now it's working fine or not within one hour(Time limit)?? ...

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SystemVerilog

#systemverilog #uvm

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