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Last pushback in queue in scoreboard write method, overriding all values in queue

Posted by possible on Dec 9, 2020
UVM #uvm #UVM #scoreboard UVM monitor #queues #systemverilog I have a monitor and a scoreboard connected through uvm_analysis_port/imp. I am sampling some values in the monitor and using the write function to transport those to the scoreboard. The scorebo ...

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UVM

#uvm #UVM #scoreboard UVM monitor #queues #systemverilog
Ways to reduce simulation time?

Posted by possible on Dec 3, 2020
UVM #uvm #systemverilog simulation How can we reduce simulation time, in general? You can list out things like- 1) Writing better constraints, for example, whatever can be done in post_randomize(), avoid it in do via constraints. ...

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UVM

#uvm #systemverilog simulation
how to implement UVM testbench for DUT VHDL?

Posted by Kiruth on Nov 27, 2020
UVM VHDL #uvm #UVM #modelsim I have a VHDL dut and I want to build a UVM testbench, I want to know: 1- Can UVM work with VHDL design? 2- Is it possible to use Modelsim Student Version or Vivado 2020? ...

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UVM

VHDL #uvm #UVM #modelsim
Interview Questions on UVM

Posted by Subbi Reddy on Nov 26, 2020
UVM #uvm #systemverilog I faced conflict to answer for the below Queries in interview,Please give knowledge in the below listed Queries: 1. don’t want to register a sequence to sequencer. What is the alternate macro to uvm_sequence_utils() macro? 2. For d ...

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UVM

#uvm #systemverilog
How driver will request each time to sequencer or sequence need different sequence_item on same interface

Posted by Subbi Reddy on Nov 26, 2020
UVM #uvm #systemverilog How driver will request each time to sequencer or sequence need different sequence_item on same interface ...

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UVM

#uvm #systemverilog
How to run multiple testcases in single run?

Posted by Manirama on Nov 25, 2020
UVM #uvm The below link can be used to run any one testcase at time (write_test or read_test or mem_wr_rd_test wr_rd_test). how to run all testcases at a time. https://www.edaplayground.com/x/2arP Please help. ...

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UVM

#uvm
Interview Questions on Systemverilog

Posted by Subbi Reddy on Nov 21, 2020
SystemVerilog #systemverilog #uvm I faced conflict to answer for the below Queries in interview,Please give knowledge in the below listed Queries: 1. I have a multi dimensional array. don’t know the number of dimensional it has. How to know the number of ...

Question
SystemVerilog

#systemverilog #uvm
Using uvm_config_db in sequence

Posted by UVM_SV_101 on Nov 19, 2020
UVM #uvm #uvm_config_db Hi, I am curious to know how uvm_config_db works to send item from component class to object class. Since component and object class have no visibility to each others hierarchy, how does set-get method work across the classes? I tr ...

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UVM

#uvm #uvm_config_db
Where to place sample_values() for getting coverage in UVM RAL?

Posted by Keiichi McGuire on Nov 17, 2020
UVM #uvm #UVM #RAL As a brute force method, I can call sample_values() inside an always block @(posedge clk). However, this is not very performance efficient. I'm not quite clear on how a RAL's built in write()/read() API call goes through, but ...

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UVM

#uvm #UVM #RAL
DUT Speed calculation

Posted by Subbi Reddy on Nov 13, 2020
UVM #uvm How to Know Input and output Speed of the DUT?? ...

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UVM

#uvm

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