Forum Search | Verification Academy

Results

Re: What is a valid Argument to run_test()

Posted by Rahulkumar on Jan 11, 2020
In reply to Have_A_Doubt: It won't generate error. did you check the code of uvm_agent and uvm_test? Both of these class are extended from the uvm_component. These classes are just wrapper over the uvm_component class. They don't contain any spe ...

Reply
UVM

valid Argument to run_test()
Re: APB Dual Timer VIP

Posted by mdzaheer92 on Jan 11, 2020
In reply to chr_sue: hi, I am looking solution for apb timer vip, how to write test case with interrupt generation for periodic/oneshot and free running modes ...

Reply
UVM

apb
Cross model reference

Posted by venkatasubbarao sutrave on Jan 11, 2020
UVM #systemverilog #UVM can anyone please inform me why am I getting the Your text to link here... following error Your text to link here... Error-[XMRE] Cross-module reference resolution error test.sv, 18 Error found while trying to resolve cross-module ...

Question
UVM

#systemverilog #UVM
Re: Cross model reference

Posted by chr_sue on Jan 11, 2020
In reply to Rahulkumar Patel: You are using UVM-1.2 but you are coding in OVM syntax. In UVM we are using build_phase, connect_phase, run_phase instead of buil, connect, run. You should clean-up your code. BTW it is running for me. See the code here: http ...

Reply
UVM

#systemverilog #UVM
Re: Cross model reference

Posted by Rahulkumar on Jan 10, 2020
In reply to venkatasubbarao sutrave: you are using the cfg handle inside the test class which isn't created in the class. I fix some of the issues but still long way to go. you are using some of the deprecated items also. https://www.edaplayground.co ...

Reply
UVM

#systemverilog #UVM
UVM_DO_ON_WITH Error

Posted by as1494 on Jan 10, 2020
UVM Hi, I am trying uvm_do_on_with to run i2c sequence on master sequencer and getting below syntax error. Can you please help on this? SEQUENCE CODE------------------------------------------------------------------------------------------------------ // ...

Question
UVM
Re: UVM_DO_ON_WITH Error

Posted by ktmills on Jan 10, 2020
In reply to as1494: You have a comma instead of a dot in the last two constraint lines between i2c_mst_seq and lcl. ...

Reply
UVM
Re: UVM_DO_ON_WITH Error

Posted by as1494 on Jan 10, 2020
In reply to chr_sue: I added sequence code and syntax error comes at uvm_do_on_with line- task body(); `uvm_do_on_with(i2c_mst_seq,m_env.i2c_env.i2c_system_env.sequencer.master_sequencer[0], {i2c_mst_seq.lcl_cmd == `SVT_I2C_WRITE; i2c_mst_seq.lcl_addr == ...

Reply
UVM
Re: UVM_DO_ON_WITH Error

Posted by chr_sue on Jan 10, 2020
In reply to as1494: You are showing only the error message. We do not see the source code, especially the sequence code. This does not allow to give you a good advice. ...

Reply
UVM
Confusion regarding create_map() of uvm_reg_block

Posted by MICRO_91 on Jan 10, 2020
UVM Confcreate_map() of uvm_reg_block Hi, I was going through UVM Cookbook:: Register Blocks function uvm_reg_map create_map (string name, // Name of the map handle uvm_reg_addr_t base_addr, // base address int unsigned n_bytes, // access width in bytes u ...

Question
UVM

Confcreate_map() of uvm_reg_block

Pages