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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
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    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
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      • Occurrence Property Patterns
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      • Start Here - Patterns Library Overview
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  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
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      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
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      • Package/Organization
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      • SystemVerilog Guidelines
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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Formal Verification Part 1 - August 20th
      • Formal Verification Part 2 - September 1st
      • User2User MARLUG
      • Events Calendar

    • On Demand Seminars

      • Improving Your SystemVerilog Language and UVM Methodology Skills
      • Visualizer Debug Environment
      • What’s New in Functional Verification from Mentor - Spring 2020
      • All On-Demand Seminars

    • Recording Archive

      • DVCon 2020 - Featured Presentations
      • DAC 2019 Session Recordings
      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • UVM Framework
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • Questa Simulation Coverage Acceleration Apps with inFact
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

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      • Verification Horizons - July 2020
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Ask a Question
UVM
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Results

  1. Re: interface class in UVM objects

    Posted by shimonc on Jul 26, 2020
    But then I will not be able to construct the child's using function new (string name = "child") super.name (name); endfunction Because virtual class cant have a constructor. But I do need that 'child' extend uvm_object. ...

    Reply
    UVM

  2. Re: Send a value from driver to monitor without using TLMs

    Posted by puttasatish on Jul 26, 2020
    Hi, You can plan to use uvm_queue or uvm_pool to achieve this. To know more about uvm_queue, you can follow the below thread. https://verificationacademy.com/forums/uvm/uvm-queue-class Hope this helps. Putta Satish ...

    Reply
    UVM
    driver monitor

  3. scoreboard design for packets arriving OOO from the DUT

    Posted by n347 on Jul 26, 2020
    UVM Scoreboard design for the following requirement: 1. Packets coming in to DUT (addr/data/enable) come out Out of order, but the packets with same addr should come out in order. 2. And also when enable =1 in the incoming packet, all the previous packets ...

    Question
    UVM

  4. Re: scoreboard design for packets arriving OOO from the DUT

    Posted by chr_sue on Jul 26, 2020
    In reply to n347: What I was saying is you can do the compare in the sequence itself and not in the scoreboard. For reading you are sending back responses from the driver to the sequence. This allows you to compare the written data (stored in an assiciati ...

    Reply
    UVM

  5. Re: Send a value from driver to monitor without using TLMs

    Posted by dave_59 on Jul 25, 2020
    In reply to Curious_cat: Use of static variables is generally discouraged is software programming. It becomes difficult to scale once you find you need multiple instances of the same environment. As you've already discovered, synchronization of readi ...

    Reply
    UVM
    driver monitor

  6. Re: Send a value from driver to monitor without using TLMs

    Posted by Curious_cat on Jul 25, 2020
    In reply to chr_sue: Quote: In reply to Curious_cat: The UVM does not have compliance rulre, i.e. you can do anything you want to do. In a few of my industrial projects I used this connection to transmit seq_items to the monitor for further processing in ...

    Reply
    UVM
    driver monitor

  7. Re: Send a value from driver to monitor without using TLMs

    Posted by Curious_cat on Jul 25, 2020
    In reply to dave_59: Thanks for all the suggestions Dave. I will see which option is best suited for my need and use it. ...

    Reply
    UVM
    driver monitor

  8. Re: scoreboard design for packets arriving OOO from the DUT

    Posted by n347 on Jul 25, 2020
    In reply to chr_sue: Can you provide an example? How would you do the check in the sequence? 1. Packets coming in to DUT (addr/data/enable) come out Out of order, but the packets with same addr should come out in order. The above check has to be performed ...

    Reply
    UVM

  9. Re: scoreboard design for packets arriving OOO from the DUT

    Posted by chr_sue on Jul 25, 2020
    In reply to n347: I see, but looks quite complicated. Could you do the compare somewhere else? A few years ago I had a DDR4 UVM testbench. I did the compare in the sequence using an associative array. Would this be an option? ...

    Reply
    UVM

  10. Re: scoreboard design for packets arriving OOO from the DUT

    Posted by n347 on Jul 25, 2020
    In reply to chr_sue: Thanks! I wanted to create a queue of associative array for a particular address. There can be many packets from a particular address, they should be in order. txn txn_aa[int]-> this will just be 1 txn per address ...

    Reply
    UVM

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