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UVM Coverage

Posted by rag123 on Apr 23, 2021
UVM #uvm Hi, 1) What is the right syntax for defining bins in coverage for enum? The below syntax doesnt seem to compile. typedef enum {READ, WRITE} kind_e; READ_WRITE: coverpoint trans.apb_cmd {bins apb_cmd [] = {[trans.apb_cmd. first: trans.apb_cmd. l ...

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UVM

#uvm
Re: UVM Coverage

Posted by chr_sue on Apr 23, 2021
In reply to rag123: Your testbench works perfectly Even without running the read sequence you get 100% functional cobverage. Look to your monitor. I was adding in your diagnostic message in the monitor the apb_cmd and this shows your are sending also READ ...

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UVM

#uvm
UVM_FATAL:: " Attempting to register a null object with the Factory "

Posted by MICRO_91 on Apr 22, 2021
UVM Attempting to register a null object with the Factory I am trying to understand output of following code:: `include "uvm_macros.svh" `include "uvm_pkg.sv" import uvm_pkg::*; class user_seq_item extends uvm_sequence_item; loca ...

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UVM

Attempting to register a null object with the Factory
Re: UVM_FATAL:: " Attempting to register a null object with the Factory "

Posted by chr_sue on Apr 22, 2021
In reply to MICRO_91: (A1): Because your driver is parameterized twice you need an individual get_type function, returning the type of the 1st parameter. (A2) Instead of running main_phase you should run run_phase. You can implement there the objection me ...

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UVM

Attempting to register a null object with the Factory
Uvm Ral

Posted by Om Ganesh B k on Apr 22, 2021
UVM Hai I am trying to understand set_check_on_read(1) in Ral. If iam enabled this means how it will check and How we can ensure this function is checking true or false. can any one explain with code how to use this in correct manner. thanks in advancee. ...

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UVM
Re: Uvm Ral

Posted by chr_sue on Apr 22, 2021
In reply to Om Ganesh B k: Please see the UVM Reference Manual. There you can read: function void set_check_on_read (bit on = 1) Sets the check-on-read mode for his map and all of its submaps. When on is TRUE, the register model will automatically check a ...

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UVM
Re: Cookbook:: Configuring Per Sequence

Posted by dave_59 on Apr 21, 2021
In reply to TC_2017: When doing multiple calls to uvm_config_db::set() from the same component, last write wins. In [Q1] The first set() is broadcast to "agent1*", then the second set() is a more specific string "agent1.seqr_h.error*". ...

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UVM

Cookbook :: Configuring Per Sequence
UVM Register Model with mixed width registers

Posted by dbrown123 on Apr 21, 2021
UVM Hi, I'm struggling with something in my UVM register model. I'm fairly new to UVM, so likely overlooking something easy. The situation is this: I have a 64-bit AHB interface to my registers. The registers are a mixture of 64-bit wide registe ...

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UVM
Re: UVM Register Model with mixed width registers

Posted by megamind on Apr 21, 2021
In reply to megamind: Also response provided by chr_sue makes sense, where you can conditionally fetch the required map to drive transactions, but again you will need condition in your adapter at least for one of the case where register is 64 bit and you ...

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UVM
Re: UVM Register Model with mixed width registers

Posted by megamind on Apr 21, 2021
In reply to pavankumark10: Pavan, when you use 8 bytes map, you need conditional transaction fields updates in your adapter. Something like below, for example for AXI, transfer.addr = rw.addr; if (rw.n_bits == 64) begin transfer.length = 1; transfer.data ...

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UVM

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