Forum Search | Verification Academy

Results

Can we set a config db in sequence body() method and get it in scoreboard?

Posted by Subhra Bera on Apr 12, 2020
UVM uvm_config_db #uvm uvm_config_db #(...)::get() Can we set a config db in sequence body() method and get it in scoreboard? I know that we have to set config db in build phase. But is it possible? ...

Question
UVM

uvm_config_db #uvm uvm_config_db #(...)::get()
Can i start parallel sequences on different sequencers in a virtual sequence?

Posted by adharshh on Apr 10, 2020
UVM virtual sequence and sequencer #uvm Hi, I am having two instances of the same agent and i am using virtual sequence approach. So if i wanted to start sequences on both the sequencers at the same time to have the driving happening at the same time,how ...

Question
UVM

virtual sequence and sequencer #uvm
what is the need of using clone for minimizing factory overrides for stimulus objects

Posted by jyotsna on Apr 7, 2020
UVM #uvm #factory #create I was referring to UVM testbench speed-up article where i found below code: //High performance code class generate_seq extends uvm_sequence # (seq_item); task body; seq_item orig_item = seq_item:: type_id:: create ("item&quo ...

Question
UVM

#uvm #factory #create
Setting a string/int inside uvm_object using UVM command line processor method

Posted by saurabh.sa27 on Mar 31, 2020
UVM Command Line Processing uvm_object #uvm class top_env extends uvm_env; //------------------------ // UVM Component Utility macro //------------------------ `uvm_component_utils_begin (top_env) `uvm_field_object (cfg, UVM_ALL_ON) `uvm_component_utils ...

Question
UVM

Command Line Processing uvm_object #uvm
get a configuration class object in interface

Posted by adharshh on Mar 9, 2020
UVM Assertions #uvm #interface Hi, Can we set-get a configuration class object from a class in an interface? I wish to write some assertions that involves making use of some configuration knobs. Is it possible? ...

Question
UVM

Assertions #uvm #interface
Test island vs Test bench

Posted by alexd555 on Mar 4, 2020
UVM #uvm Hi, I can't understand what meaning of test island? What is difference between test island and test bench? Thanks, Alex ...

Question
UVM

#uvm
Multiple lock() in parallel sequences is broken in uvm-1.2?

Posted by mitesh.patel on Mar 2, 2020
UVM #uvm Cookbook: Sequences/LockGrab Hi All, We were exploring lock/grab feature of uvm_sequencer on UVM-1.2 using below code: class instruction extends uvm_sequence_item; typedef enum {PUSH_A, PUSH_B, ADD, SUB, MUL, DIV, POP_C} inst_t; rand inst_t inst; ...

Question
UVM

#uvm Cookbook: Sequences/LockGrab
How to generate expected results in apb_scoreboard

Posted by Chandra Shekar N on Feb 18, 2020
UVM #uvm dut to scoreboard https://www.edaplayground.com/x/4gSP Hi all, In the above link bus_monitor and monitor is observing the same interface. Even any changes made to DUT doesn't result in any error. Is it possible to monitor signals given to dr ...

Question
UVM

#uvm dut to scoreboard
How to display time in femtoseconds for uvm_info statements

Posted by sj1992 on Feb 11, 2020
UVM #uvm UVM_VERBOSITY timescale uvm_info Hi, Is there is command-line option to display time in femtoseconds for uvm_info statements? At present all the uvm statements are printed out in nanoseconds Thanks ...

Question
UVM

#uvm UVM_VERBOSITY timescale uvm_info
timeout in simulation.

Posted by dvuvmsv on Feb 10, 2020
UVM #uvm Hello, I have tests which run for 2 hours long and 10 minutes long. I need to implement a timeout mechanism to prevent any runaway simulation. I cannot put a global_timeout_value of 2 hours for all tests. What is the best way to implement a timeo ...

Question
UVM

#uvm

Pages