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can an object instantiated after config_db set()?

Posted by Charlesjjj on Apr 20, 2023
UVM #uvm #uvm_config_db #systemverilog Null pointer dereference hi, can someone tell me if i want to send an object via config_db, does is matter if i new() it before or after config_db set()? When i ran my code. i found if i do config_db set(), then do n ...

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UVM

#uvm #uvm_config_db #systemverilog Null pointer dereference
Using get_next_item and item_done methods in the driver With/Without RSP packet

Posted by UVM_LOVE on Apr 20, 2023
UVM get_response UVM Hi, I'm quite a bit confused about the using get_next_item and item_done methods in the driver With/Without RSP packet. Basically, one of the approach in Sequence-Driver-Sequencer communication is the using get_next_item and item ...

Question
UVM

get_response UVM
How to gracefully end the test before main phase in UVM

Posted by irshad_mansur on Apr 20, 2023
UVM Hi, In my test based on certain condition I want to end my test in configure_phase itself. Is there anyway to do that. I don't want to set the flag and do if else if else in all remaining phases to skip them. Thanks, ...

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UVM
UVM catcher to grep for UVM_ERROR message

Posted by MP on Apr 20, 2023
UVM Hello UVM Gurus, Can someone guide me how does catcher in the UVM grep for uvm_error message? ...

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UVM
Unified Verification Environment

Posted by uvm_share on Apr 20, 2023
UVM uvm_env UVM #coverage #UVM #scoreboard Im trying to find the right structure for developing a unified verification environment for some bridges (6 bridges) for that: 1) I will have one generic scoreboard, env_top, test, and tb_top 2) The agents of thi ...

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UVM

uvm_env UVM #coverage #UVM #scoreboard
what is relationship of run_phase and main_phase?

Posted by ppeezz on Apr 19, 2023
UVM UVM phase objection I am confused with the relationship of run_phase and main_phase. so I do a experiment. I used run_phase and main_phase in different component. when I run the flowing code, I found the code of main_phase in sys_env do not execute. w ...

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UVM

UVM phase objection
Can I use base class object in the extend class?

Posted by UVM_LOVE on Apr 19, 2023
UVM I'm trying to use one object which is declared in base class and I want to use it under extend class. Can I use a base class's object under the extend class? For example, //TEST Class. class my_base_test extends uvm_test;... function void bu ...

Question
UVM
Transaction Packet to Pin level?

Posted by Yeptho on Apr 19, 2023
UVM Transactionpacket to wiggling pins If I'm not wrong, how transaction Packet from agent(driver/monitor) are converted to wiggling pin level(& vice versa) via interface to DUT? I'm cerebrate how things are done in the UVM env. ...

Question
UVM

Transactionpacket to wiggling pins
driving clock and data from sequence

Posted by new_uvm_user on Apr 18, 2023
UVM Hi, I want to drive data and clock from sequence. sequence item: class inv_transaction extends uvm_sequence_item; `uvm_object_utils (inv_transaction) function new (string name = "inv_transaction"); super. new (name); endfunction bit a; bit ...

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UVM
Config_db set and get method

Posted by Rana Adeel Ahmad on Apr 18, 2023
UVM Well i am having a problem using set and get method. Using set method of config-db a class is set in the interface. the code is: uvm_config_db # (uvm_object):: set (null, "*", "accessor_drv", drv_acc); But when i am trying to get t ...

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UVM

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